Equations

********** Mapped Logic **********
FDCPE_Led0: FDCPE port map (Led(0),Led_D(0),Clk,'0','0');
     Led_D(0) <= (Reset AND DipSwitch(0));
FDCPE_Led1: FDCPE port map (Led(1),Led_D(1),Clk,'0','0');
     Led_D(1) <= (Reset AND DipSwitch(1));
FDCPE_Led2: FDCPE port map (Led(2),Led_D(2),Clk,'0','0');
     Led_D(2) <= (Reset AND DipSwitch(2));
FDCPE_Led3: FDCPE port map (Led(3),Led_D(3),Clk,'0','0');
     Led_D(3) <= (Reset AND DipSwitch(3));
FDCPE_Led4: FDCPE port map (Led(4),Led_D(4),Clk,'0','0');
     Led_D(4) <= (Reset AND DipSwitch(4));
FDCPE_Led5: FDCPE port map (Led(5),Led_D(5),Clk,'0','0');
     Led_D(5) <= (Reset AND DipSwitch(5));
FDCPE_Led6: FDCPE port map (Led(6),Led_D(6),Clk,'0','0');
     Led_D(6) <= (Reset AND DipSwitch(6));
FDCPE_Led7: FDCPE port map (Led(7),Led_D(7),Clk,'0','0');
     Led_D(7) <= (Reset AND DipSwitch(7));
Register Legend:
      FDCPE (Q,D,C,CLR,PRE,CE);
      FTCPE (Q,D,C,CLR,PRE,CE);
      LDCP (Q,D,G,CLR,PRE);