Timing Report

Need help reading this report?

Design Name BoardTest
Device, Speed (SpeedFile Version) XC9536XL, -5 (3.0)
Date Created Mon Jul 07 22:45:14 2008
Created By Timing Report Generator: version K.37
Copyright Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved.

Summary

Notes and Warnings
Note: This design contains no timing constraints.
Note: A default set of constraints using a delay of 0.000ns will be used for analysis.

Performance Summary
Min. Clock Period 5.600 ns.
Max. Clock Frequency (fSYSTEM) 178.571 MHz.
Limited by Clock Pulse Width for Clk
Setup to Clock at the Pad (tSU) 3.700 ns.
Clock Pad to Output Pad Delay (tCO) 3.500 ns.

Timing Constraints

Constraint Name Requirement (ns) Delay (ns) Paths Paths Failing
TS1000 0.0 0.0 0 0
AUTO_TS_F2F 0.0 0.0 0 0
AUTO_TS_P2P 0.0 3.5 8 8
AUTO_TS_P2F 0.0 4.8 17 17
AUTO_TS_F2P 0.0 2.4 8 8


Constraint: TS1000

Description: PERIOD:PERIOD_Clk:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: AUTO_TS_F2F

Description: MAXDELAY:FROM:FFS(*):TO:FFS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: AUTO_TS_P2P

Description: MAXDELAY:FROM:PADS(*):TO:PADS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
Clk to Led<0> 0.000 3.500 -3.500
Clk to Led<1> 0.000 3.500 -3.500
Clk to Led<2> 0.000 3.500 -3.500


Constraint: AUTO_TS_P2F

Description: MAXDELAY:FROM:PADS(*):TO:FFS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
DipSwitch<0> to Led<0>.D 0.000 4.800 -4.800
DipSwitch<1> to Led<1>.D 0.000 4.800 -4.800
DipSwitch<2> to Led<2>.D 0.000 4.800 -4.800


Constraint: AUTO_TS_F2P

Description: MAXDELAY:FROM:FFS(*):TO:PADS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
Led<0>.Q to Led<0> 0.000 2.400 -2.400
Led<1>.Q to Led<1> 0.000 2.400 -2.400
Led<2>.Q to Led<2> 0.000 2.400 -2.400



Number of constraints not met: 3

Data Sheet Report

Maximum External Clock Speeds

Clock fEXT (MHz) Reason
Clk 178.571 Limited by Clock Pulse Width for Clk

Setup/Hold Times for Clocks

Setup/Hold Times for Clock Clk
Source Pad Setup to clk (edge) Hold to clk (edge)
DipSwitch<0> 3.700 0.000
DipSwitch<1> 3.700 0.000
DipSwitch<2> 3.700 0.000
DipSwitch<3> 3.700 0.000
DipSwitch<4> 3.700 0.000
DipSwitch<5> 3.700 0.000
DipSwitch<6> 3.700 0.000
DipSwitch<7> 3.700 0.000
Reset 3.700 0.000


Clock to Pad Timing

Clock Clk to Pad
Destination Pad Clock (edge) to Pad
Led<0> 3.500
Led<1> 3.500
Led<2> 3.500
Led<3> 3.500
Led<4> 3.500
Led<5> 3.500
Led<6> 3.500
Led<7> 3.500


Clock to Setup Times for Clocks


Pad to Pad List

Source Pad Destination Pad Delay



Number of paths analyzed: 33
Number of Timing errors: 33
Analysis Completed: Mon Jul 07 22:45:14 2008