********** Mapped Logic ********** |
FTCPE_Devided_Clk: FTCPE port map (Devided_Clk,'1',Clk,NOT Reset,'0',Devided_Clk_CE);
Devided_Clk_CE <= (NOT U1/uDevideCount(0) AND U1/uDevideCount(10) AND NOT U1/uDevideCount(11) AND NOT U1/uDevideCount(12) AND NOT U1/uDevideCount(13) AND NOT U1/uDevideCount(14) AND U1/uDevideCount(15) AND NOT U1/uDevideCount(1) AND NOT U1/uDevideCount(2) AND NOT U1/uDevideCount(3) AND NOT U1/uDevideCount(4) AND U1/uDevideCount(5) AND NOT U1/uDevideCount(6) AND U1/uDevideCount(7) AND NOT U1/uDevideCount(8) AND U1/uDevideCount(9) AND U1/uDevideCount(16)); |
FDCPE_Led0: FDCPE port map (Led(0),Led_D(0),NOT Devided_Clk,'0','0');
Led_D(0) <= ((Reset AND Led(7)) OR (NOT Reset AND DipSwitch(0))); |
FDCPE_Led1: FDCPE port map (Led(1),Led_D(1),NOT Devided_Clk,'0','0');
Led_D(1) <= ((Reset AND Led(0)) OR (NOT Reset AND DipSwitch(1))); |
FDCPE_Led2: FDCPE port map (Led(2),Led_D(2),NOT Devided_Clk,'0','0');
Led_D(2) <= ((Reset AND Led(1)) OR (NOT Reset AND DipSwitch(2))); |
FDCPE_Led3: FDCPE port map (Led(3),Led_D(3),NOT Devided_Clk,'0','0');
Led_D(3) <= ((Reset AND Led(2)) OR (NOT Reset AND DipSwitch(3))); |
FDCPE_Led4: FDCPE port map (Led(4),Led_D(4),NOT Devided_Clk,'0','0');
Led_D(4) <= ((Reset AND Led(3)) OR (NOT Reset AND DipSwitch(4))); |
FDCPE_Led5: FDCPE port map (Led(5),Led_D(5),NOT Devided_Clk,'0','0');
Led_D(5) <= ((Reset AND Led(4)) OR (NOT Reset AND DipSwitch(5))); |
FDCPE_Led6: FDCPE port map (Led(6),Led_D(6),NOT Devided_Clk,'0','0');
Led_D(6) <= ((Reset AND Led(5)) OR (NOT Reset AND DipSwitch(6))); |
FDCPE_Led7: FDCPE port map (Led(7),Led_D(7),NOT Devided_Clk,'0','0');
Led_D(7) <= ((Reset AND Led(6)) OR (NOT Reset AND DipSwitch(7))); |
FTCPE_U1/uDevideCount0: FTCPE port map (U1/uDevideCount(0),U1/uDevideCount_T(0),Clk,NOT Reset,'0');
U1/uDevideCount_T(0) <= (NOT U1/uDevideCount(0) AND U1/uDevideCount(10) AND NOT U1/uDevideCount(11) AND NOT U1/uDevideCount(12) AND NOT U1/uDevideCount(13) AND NOT U1/uDevideCount(14) AND U1/uDevideCount(15) AND NOT U1/uDevideCount(1) AND NOT U1/uDevideCount(2) AND NOT U1/uDevideCount(3) AND NOT U1/uDevideCount(4) AND U1/uDevideCount(5) AND NOT U1/uDevideCount(6) AND U1/uDevideCount(7) AND NOT U1/uDevideCount(8) AND U1/uDevideCount(9) AND U1/uDevideCount(16)); |
FTCPE_U1/uDevideCount1: FTCPE port map (U1/uDevideCount(1),U1/uDevideCount(0),Clk,NOT Reset,'0'); |
FTCPE_U1/uDevideCount2: FTCPE port map (U1/uDevideCount(2),U1/uDevideCount_T(2),Clk,NOT Reset,'0');
U1/uDevideCount_T(2) <= (U1/uDevideCount(0) AND U1/uDevideCount(1)); |
FTCPE_U1/uDevideCount3: FTCPE port map (U1/uDevideCount(3),U1/uDevideCount_T(3),Clk,NOT Reset,'0');
U1/uDevideCount_T(3) <= (U1/uDevideCount(0) AND U1/uDevideCount(1) AND U1/uDevideCount(2)); |
FTCPE_U1/uDevideCount4: FTCPE port map (U1/uDevideCount(4),U1/uDevideCount_T(4),Clk,NOT Reset,'0');
U1/uDevideCount_T(4) <= (U1/uDevideCount(0) AND U1/uDevideCount(1) AND U1/uDevideCount(2) AND U1/uDevideCount(3)); |
FTCPE_U1/uDevideCount5: FTCPE port map (U1/uDevideCount(5),U1/uDevideCount_T(5),Clk,NOT Reset,'0');
U1/uDevideCount_T(5) <= ((U1/uDevideCount(0) AND U1/uDevideCount(1) AND U1/uDevideCount(2) AND U1/uDevideCount(3) AND U1/uDevideCount(4)) OR (NOT U1/uDevideCount(0) AND U1/uDevideCount(10) AND NOT U1/uDevideCount(11) AND NOT U1/uDevideCount(12) AND NOT U1/uDevideCount(13) AND NOT U1/uDevideCount(14) AND U1/uDevideCount(15) AND NOT U1/uDevideCount(1) AND NOT U1/uDevideCount(2) AND NOT U1/uDevideCount(3) AND NOT U1/uDevideCount(4) AND U1/uDevideCount(5) AND NOT U1/uDevideCount(6) AND U1/uDevideCount(7) AND NOT U1/uDevideCount(8) AND U1/uDevideCount(9) AND U1/uDevideCount(16))); |
FTCPE_U1/uDevideCount6: FTCPE port map (U1/uDevideCount(6),U1/uDevideCount_T(6),Clk,NOT Reset,'0');
U1/uDevideCount_T(6) <= (U1/uDevideCount(0) AND U1/uDevideCount(1) AND U1/uDevideCount(2) AND U1/uDevideCount(3) AND U1/uDevideCount(4) AND U1/uDevideCount(5)); |
FTCPE_U1/uDevideCount7: FTCPE port map (U1/uDevideCount(7),U1/uDevideCount_T(7),Clk,NOT Reset,'0');
U1/uDevideCount_T(7) <= ((U1/uDevideCount(0) AND U1/uDevideCount(1) AND U1/uDevideCount(2) AND U1/uDevideCount(3) AND U1/uDevideCount(4) AND U1/uDevideCount(5) AND U1/uDevideCount(6)) OR (NOT U1/uDevideCount(0) AND U1/uDevideCount(10) AND NOT U1/uDevideCount(11) AND NOT U1/uDevideCount(12) AND NOT U1/uDevideCount(13) AND NOT U1/uDevideCount(14) AND U1/uDevideCount(15) AND NOT U1/uDevideCount(1) AND NOT U1/uDevideCount(2) AND NOT U1/uDevideCount(3) AND NOT U1/uDevideCount(4) AND U1/uDevideCount(5) AND NOT U1/uDevideCount(6) AND U1/uDevideCount(7) AND NOT U1/uDevideCount(8) AND U1/uDevideCount(9) AND U1/uDevideCount(16))); |
FTCPE_U1/uDevideCount8: FTCPE port map (U1/uDevideCount(8),U1/uDevideCount_T(8),Clk,NOT Reset,'0');
U1/uDevideCount_T(8) <= (U1/uDevideCount(0) AND U1/uDevideCount(1) AND U1/uDevideCount(2) AND U1/uDevideCount(3) AND U1/uDevideCount(4) AND U1/uDevideCount(5) AND U1/uDevideCount(6) AND U1/uDevideCount(7)); |
FTCPE_U1/uDevideCount9: FTCPE port map (U1/uDevideCount(9),U1/uDevideCount_T(9),Clk,NOT Reset,'0');
U1/uDevideCount_T(9) <= ((U1/uDevideCount(0) AND U1/uDevideCount(1) AND U1/uDevideCount(2) AND U1/uDevideCount(3) AND U1/uDevideCount(4) AND U1/uDevideCount(5) AND U1/uDevideCount(6) AND U1/uDevideCount(7) AND U1/uDevideCount(8)) OR (NOT U1/uDevideCount(0) AND U1/uDevideCount(10) AND NOT U1/uDevideCount(11) AND NOT U1/uDevideCount(12) AND NOT U1/uDevideCount(13) AND NOT U1/uDevideCount(14) AND U1/uDevideCount(15) AND NOT U1/uDevideCount(1) AND NOT U1/uDevideCount(2) AND NOT U1/uDevideCount(3) AND NOT U1/uDevideCount(4) AND U1/uDevideCount(5) AND NOT U1/uDevideCount(6) AND U1/uDevideCount(7) AND NOT U1/uDevideCount(8) AND U1/uDevideCount(9) AND U1/uDevideCount(16))); |
FTCPE_U1/uDevideCount10: FTCPE port map (U1/uDevideCount(10),U1/uDevideCount_T(10),Clk,NOT Reset,'0');
U1/uDevideCount_T(10) <= ((U1/uDevideCount(0) AND U1/uDevideCount(1) AND U1/uDevideCount(2) AND U1/uDevideCount(3) AND U1/uDevideCount(4) AND U1/uDevideCount(5) AND U1/uDevideCount(6) AND U1/uDevideCount(7) AND U1/uDevideCount(8) AND U1/uDevideCount(9)) OR (NOT U1/uDevideCount(0) AND U1/uDevideCount(10) AND NOT U1/uDevideCount(11) AND NOT U1/uDevideCount(12) AND NOT U1/uDevideCount(13) AND NOT U1/uDevideCount(14) AND U1/uDevideCount(15) AND NOT U1/uDevideCount(1) AND NOT U1/uDevideCount(2) AND NOT U1/uDevideCount(3) AND NOT U1/uDevideCount(4) AND U1/uDevideCount(5) AND NOT U1/uDevideCount(6) AND U1/uDevideCount(7) AND NOT U1/uDevideCount(8) AND U1/uDevideCount(9) AND U1/uDevideCount(16))); |
FTCPE_U1/uDevideCount11: FTCPE port map (U1/uDevideCount(11),U1/uDevideCount_T(11),Clk,NOT Reset,'0');
U1/uDevideCount_T(11) <= (U1/uDevideCount(0) AND U1/uDevideCount(10) AND U1/uDevideCount(1) AND U1/uDevideCount(2) AND U1/uDevideCount(3) AND U1/uDevideCount(4) AND U1/uDevideCount(5) AND U1/uDevideCount(6) AND U1/uDevideCount(7) AND U1/uDevideCount(8) AND U1/uDevideCount(9)); |
FTCPE_U1/uDevideCount12: FTCPE port map (U1/uDevideCount(12),U1/uDevideCount_T(12),Clk,NOT Reset,'0');
U1/uDevideCount_T(12) <= (U1/uDevideCount(0) AND U1/uDevideCount(10) AND U1/uDevideCount(11) AND U1/uDevideCount(1) AND U1/uDevideCount(2) AND U1/uDevideCount(3) AND U1/uDevideCount(4) AND U1/uDevideCount(5) AND U1/uDevideCount(6) AND U1/uDevideCount(7) AND U1/uDevideCount(8) AND U1/uDevideCount(9)); |
FTCPE_U1/uDevideCount13: FTCPE port map (U1/uDevideCount(13),U1/uDevideCount_T(13),Clk,NOT Reset,'0');
U1/uDevideCount_T(13) <= (U1/uDevideCount(0) AND U1/uDevideCount(10) AND U1/uDevideCount(11) AND U1/uDevideCount(12) AND U1/uDevideCount(1) AND U1/uDevideCount(2) AND U1/uDevideCount(3) AND U1/uDevideCount(4) AND U1/uDevideCount(5) AND U1/uDevideCount(6) AND U1/uDevideCount(7) AND U1/uDevideCount(8) AND U1/uDevideCount(9)); |
FTCPE_U1/uDevideCount14: FTCPE port map (U1/uDevideCount(14),U1/uDevideCount_T(14),Clk,NOT Reset,'0');
U1/uDevideCount_T(14) <= (U1/uDevideCount(0) AND U1/uDevideCount(10) AND U1/uDevideCount(11) AND U1/uDevideCount(12) AND U1/uDevideCount(13) AND U1/uDevideCount(1) AND U1/uDevideCount(2) AND U1/uDevideCount(3) AND U1/uDevideCount(4) AND U1/uDevideCount(5) AND U1/uDevideCount(6) AND U1/uDevideCount(7) AND U1/uDevideCount(8) AND U1/uDevideCount(9)); |
FTCPE_U1/uDevideCount15: FTCPE port map (U1/uDevideCount(15),U1/uDevideCount_T(15),Clk,NOT Reset,'0');
U1/uDevideCount_T(15) <= ((U1/uDevideCount(0) AND U1/uDevideCount(10) AND U1/uDevideCount(11) AND U1/uDevideCount(12) AND U1/uDevideCount(13) AND U1/uDevideCount(14) AND U1/uDevideCount(1) AND U1/uDevideCount(2) AND U1/uDevideCount(3) AND U1/uDevideCount(4) AND U1/uDevideCount(5) AND U1/uDevideCount(6) AND U1/uDevideCount(7) AND U1/uDevideCount(8) AND U1/uDevideCount(9)) OR (NOT U1/uDevideCount(0) AND U1/uDevideCount(10) AND NOT U1/uDevideCount(11) AND NOT U1/uDevideCount(12) AND NOT U1/uDevideCount(13) AND NOT U1/uDevideCount(14) AND U1/uDevideCount(15) AND NOT U1/uDevideCount(1) AND NOT U1/uDevideCount(2) AND NOT U1/uDevideCount(3) AND NOT U1/uDevideCount(4) AND U1/uDevideCount(5) AND NOT U1/uDevideCount(6) AND U1/uDevideCount(7) AND NOT U1/uDevideCount(8) AND U1/uDevideCount(9) AND U1/uDevideCount(16))); |
FTCPE_U1/uDevideCount16: FTCPE port map (U1/uDevideCount(16),U1/uDevideCount_T(16),Clk,NOT Reset,'0');
U1/uDevideCount_T(16) <= ((U1/uDevideCount(0) AND U1/uDevideCount(10) AND U1/uDevideCount(11) AND U1/uDevideCount(12) AND U1/uDevideCount(13) AND U1/uDevideCount(14) AND U1/uDevideCount(15) AND U1/uDevideCount(1) AND U1/uDevideCount(2) AND U1/uDevideCount(3) AND U1/uDevideCount(4) AND U1/uDevideCount(5) AND U1/uDevideCount(6) AND U1/uDevideCount(7) AND U1/uDevideCount(8) AND U1/uDevideCount(9)) OR (NOT U1/uDevideCount(0) AND U1/uDevideCount(10) AND NOT U1/uDevideCount(11) AND NOT U1/uDevideCount(12) AND NOT U1/uDevideCount(13) AND NOT U1/uDevideCount(14) AND U1/uDevideCount(15) AND NOT U1/uDevideCount(1) AND NOT U1/uDevideCount(2) AND NOT U1/uDevideCount(3) AND NOT U1/uDevideCount(4) AND U1/uDevideCount(5) AND NOT U1/uDevideCount(6) AND U1/uDevideCount(7) AND NOT U1/uDevideCount(8) AND U1/uDevideCount(9) AND U1/uDevideCount(16))); |
Register Legend:
FDCPE (Q,D,C,CLR,PRE,CE); FTCPE (Q,D,C,CLR,PRE,CE); LDCP (Q,D,G,CLR,PRE); |