cpldfit: version K.37 Xilinx Inc. Fitter Report Design Name: BoardTest Date: 7-10-2008, 0:05AM Device Used: XC9536XL-5-VQ44 Fitting Status: Successful ************************* Mapped Resource Summary ************************** Macrocells Product Terms Function Block Registers Pins Used/Tot Used/Tot Inps Used/Tot Used/Tot Used/Tot 26 /36 ( 72%) 66 /180 ( 37%) 36 /108 ( 33%) 26 /36 ( 72%) 18 /34 ( 53%) ** Function Block Resources ** Function Mcells FB Inps Pterms IO Block Used/Tot Used/Tot Used/Tot Used/Tot FB1 18/18* 18/54 42/90 2/17 FB2 8/18 18/54 24/90 16/17 ----- ----- ----- ----- 26/36 36/108 66/180 18/34 * - Resource is exhausted ** Global Control Resources ** Signal 'Clk' mapped onto global clock net GCK1. Global output enable net(s) unused. Global set/reset net(s) unused. ** Pin Resources ** Signal Type Required Mapped | Pin Type Used Total ------------------------------------|------------------------------------ Input : 9 9 | I/O : 13 28 Output : 8 8 | GCK/IO : 2 3 Bidirectional : 0 0 | GTS/IO : 2 2 GCK : 1 1 | GSR/IO : 1 1 GTS : 0 0 | GSR : 0 0 | ---- ---- Total 18 18 ** Power Data ** There are 26 macrocells in high performance mode (MCHP). There are 0 macrocells in low power mode (MCLP). End of Mapped Resource Summary ************************** Errors and Warnings *************************** INFO:Cpld - Inferring BUFG constraint for signal 'Clk' based upon the LOC constraint 'P43'. It is recommended that you declare this BUFG explicitedly in your design. Note that for certain device families the output of a BUFG constraint can not drive a gated clock, and the BUFG constraint will be ignored. INFO:Cpld - Inferring BUFG constraint for signal 'Reset' based upon the LOC constraint 'P44'. It is recommended that you declare this BUFG explicitedly in your design. Note that for certain device families the output of a BUFG constraint can not drive a gated clock, and the BUFG constraint will be ignored. WARNING:Cpld:1007 - Removing unused input(s) 'Load'. The input(s) are unused after optimization. Please verify functionality via simulation. WARNING:Cpld:1239 - The global clock designation (BUFG) on signal 'Reset_IBUF' is ignored. Most likely the signal is gated and therefore cannot be used as a global control signal. ************************* Summary of Mapped Logic ************************ ** 8 Outputs ** Signal Total Total Loc Pin Pin Pin Pwr Slew Reg Init Name Pts Inps No. Type Use Mode Rate State Led<0> 3 4 FB2_7 32 I/O O STD FAST RESET Led<1> 3 4 FB2_8 31 I/O O STD FAST RESET Led<2> 3 4 FB2_9 30 I/O O STD FAST RESET Led<3> 3 4 FB2_10 29 I/O O STD FAST RESET Led<4> 3 4 FB2_11 28 I/O O STD FAST RESET Led<5> 3 4 FB2_12 27 I/O O STD FAST RESET Led<6> 3 4 FB2_13 23 I/O O STD FAST RESET Led<7> 3 4 FB2_14 22 I/O O STD FAST RESET ** 18 Buried Nodes ** Signal Total Total Loc Pwr Reg Init Name Pts Inps Mode State U1/uDevideCount<8> 2 9 FB1_1 STD RESET U1/uDevideCount<6> 2 7 FB1_2 STD RESET U1/uDevideCount<4> 2 5 FB1_3 STD RESET U1/uDevideCount<3> 2 4 FB1_4 STD RESET U1/uDevideCount<2> 2 3 FB1_5 STD RESET U1/uDevideCount<1> 2 2 FB1_6 STD RESET U1/uDevideCount<14> 2 15 FB1_7 STD RESET U1/uDevideCount<13> 2 14 FB1_8 STD RESET U1/uDevideCount<12> 2 13 FB1_9 STD RESET U1/uDevideCount<11> 2 12 FB1_10 STD RESET U1/uDevideCount<0> 2 18 FB1_11 STD RESET Devided_Clk 2 18 FB1_12 STD RESET U1/uDevideCount<9> 3 18 FB1_13 STD RESET U1/uDevideCount<7> 3 18 FB1_14 STD RESET U1/uDevideCount<5> 3 18 FB1_15 STD RESET U1/uDevideCount<16> 3 18 FB1_16 STD RESET U1/uDevideCount<15> 3 18 FB1_17 STD RESET U1/uDevideCount<10> 3 18 FB1_18 STD RESET ** 10 Inputs ** Signal Loc Pin Pin Pin Name No. Type Use Clk FB1_3 43 GCK/I/O GCK Reset FB1_5 44 GCK/I/O I DipSwitch<1> FB2_1 39 I/O I DipSwitch<2> FB2_2 38 I/O I DipSwitch<4> FB2_3 36 GTS/I/O I DipSwitch<3> FB2_4 37 I/O I DipSwitch<5> FB2_5 34 GTS/I/O I DipSwitch<6> FB2_6 33 GSR/I/O I DipSwitch<7> FB2_15 21 I/O I DipSwitch<0> FB2_16 20 I/O I Legend: Pin No. - ~ - User Assigned ************************** Function Block Details ************************ Legend: Total Pt - Total product terms used by the macrocell signal Imp Pt - Product terms imported from other macrocells Exp Pt - Product terms exported to other macrocells in direction shown Unused Pt - Unused local product terms remaining in macrocell Loc - Location where logic was mapped in device Pin Type/Use - I - Input GCK - Global Clock O - Output GTS - Global Output Enable (b) - Buried macrocell GSR - Global Set/Reset X - Signal used as input to the macrocell logic. Pin No. - ~ - User Assigned *********************************** FB1 *********************************** Number of function block inputs used/remaining: 18/36 Number of signals used by logic mapping into function block: 18 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use U1/uDevideCount<8> 2 0 0 3 FB1_1 40 I/O (b) U1/uDevideCount<6> 2 0 0 3 FB1_2 41 I/O (b) U1/uDevideCount<4> 2 0 0 3 FB1_3 43 GCK/I/O GCK U1/uDevideCount<3> 2 0 0 3 FB1_4 42 I/O (b) U1/uDevideCount<2> 2 0 0 3 FB1_5 44 GCK/I/O I U1/uDevideCount<1> 2 0 0 3 FB1_6 2 I/O (b) U1/uDevideCount<14> 2 0 0 3 FB1_7 1 GCK/I/O (b) U1/uDevideCount<13> 2 0 0 3 FB1_8 3 I/O (b) U1/uDevideCount<12> 2 0 0 3 FB1_9 5 I/O (b) U1/uDevideCount<11> 2 0 0 3 FB1_10 6 I/O (b) U1/uDevideCount<0> 2 0 0 3 FB1_11 7 I/O (b) Devided_Clk 2 0 0 3 FB1_12 8 I/O (b) U1/uDevideCount<9> 3 0 0 2 FB1_13 12 I/O (b) U1/uDevideCount<7> 3 0 0 2 FB1_14 13 I/O (b) U1/uDevideCount<5> 3 0 0 2 FB1_15 14 I/O (b) U1/uDevideCount<16> 3 0 0 2 FB1_16 16 I/O (b) U1/uDevideCount<15> 3 0 0 2 FB1_17 18 I/O (b) U1/uDevideCount<10> 3 0 0 2 FB1_18 (b) (b) Signals Used by Logic in Function Block 1: Reset 7: U1/uDevideCount<14> 13: U1/uDevideCount<4> 2: U1/uDevideCount<0> 8: U1/uDevideCount<15> 14: U1/uDevideCount<5> 3: U1/uDevideCount<10> 9: U1/uDevideCount<16> 15: U1/uDevideCount<6> 4: U1/uDevideCount<11> 10: U1/uDevideCount<1> 16: U1/uDevideCount<7> 5: U1/uDevideCount<12> 11: U1/uDevideCount<2> 17: U1/uDevideCount<8> 6: U1/uDevideCount<13> 12: U1/uDevideCount<3> 18: U1/uDevideCount<9> Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs U1/uDevideCount<8> XX.......XXXXXXX........................ 9 U1/uDevideCount<6> XX.......XXXXX.......................... 7 U1/uDevideCount<4> XX.......XXX............................ 5 U1/uDevideCount<3> XX.......XX............................. 4 U1/uDevideCount<2> XX.......X.............................. 3 U1/uDevideCount<1> XX...................................... 2 U1/uDevideCount<14> XXXXXX...XXXXXXXXX...................... 15 U1/uDevideCount<13> XXXXX....XXXXXXXXX...................... 14 U1/uDevideCount<12> XXXX.....XXXXXXXXX...................... 13 U1/uDevideCount<11> XXX......XXXXXXXXX...................... 12 U1/uDevideCount<0> XXXXXXXXXXXXXXXXXX...................... 18 Devided_Clk XXXXXXXXXXXXXXXXXX...................... 18 U1/uDevideCount<9> XXXXXXXXXXXXXXXXXX...................... 18 U1/uDevideCount<7> XXXXXXXXXXXXXXXXXX...................... 18 U1/uDevideCount<5> XXXXXXXXXXXXXXXXXX...................... 18 U1/uDevideCount<16> XXXXXXXXXXXXXXXXXX...................... 18 U1/uDevideCount<15> XXXXXXXXXXXXXXXXXX...................... 18 U1/uDevideCount<10> XXXXXXXXXXXXXXXXXX...................... 18 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB2 *********************************** Number of function block inputs used/remaining: 18/36 Number of signals used by logic mapping into function block: 18 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB2_1 39 I/O I (unused) 0 0 0 5 FB2_2 38 I/O I (unused) 0 0 0 5 FB2_3 36 GTS/I/O I (unused) 0 0 0 5 FB2_4 37 I/O I (unused) 0 0 0 5 FB2_5 34 GTS/I/O I (unused) 0 0 0 5 FB2_6 33 GSR/I/O I Led<0> 3 0 0 2 FB2_7 32 I/O O Led<1> 3 0 0 2 FB2_8 31 I/O O Led<2> 3 0 0 2 FB2_9 30 I/O O Led<3> 3 0 0 2 FB2_10 29 I/O O Led<4> 3 0 0 2 FB2_11 28 I/O O Led<5> 3 0 0 2 FB2_12 27 I/O O Led<6> 3 0 0 2 FB2_13 23 I/O O Led<7> 3 0 0 2 FB2_14 22 I/O O (unused) 0 0 0 5 FB2_15 21 I/O I (unused) 0 0 0 5 FB2_16 20 I/O I (unused) 0 0 0 5 FB2_17 19 I/O (unused) 0 0 0 5 FB2_18 (b) Signals Used by Logic in Function Block 1: Devided_Clk 7: DipSwitch<5> 13: Led<3> 2: DipSwitch<0> 8: DipSwitch<6> 14: Led<4> 3: DipSwitch<1> 9: DipSwitch<7> 15: Led<5> 4: DipSwitch<2> 10: Led<0> 16: Led<6> 5: DipSwitch<3> 11: Led<1> 17: Led<7> 6: DipSwitch<4> 12: Led<2> 18: Reset Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs Led<0> XX..............XX...................... 4 Led<1> X.X......X.......X...................... 4 Led<2> X..X......X......X...................... 4 Led<3> X...X......X.....X...................... 4 Led<4> X....X......X....X...................... 4 Led<5> X.....X......X...X...................... 4 Led<6> X......X......X..X...................... 4 Led<7> X.......X......X.X...................... 4 0----+----1----+----2----+----3----+----4 0 0 0 0 ******************************* Equations ******************************** ********** Mapped Logic ********** FTCPE_Devided_Clk: FTCPE port map (Devided_Clk,'1',Clk,NOT Reset,'0',Devided_Clk_CE); Devided_Clk_CE <= (NOT U1/uDevideCount(0) AND U1/uDevideCount(10) AND NOT U1/uDevideCount(11) AND NOT U1/uDevideCount(12) AND NOT U1/uDevideCount(13) AND NOT U1/uDevideCount(14) AND U1/uDevideCount(15) AND NOT U1/uDevideCount(1) AND NOT U1/uDevideCount(2) AND NOT U1/uDevideCount(3) AND NOT U1/uDevideCount(4) AND U1/uDevideCount(5) AND NOT U1/uDevideCount(6) AND U1/uDevideCount(7) AND NOT U1/uDevideCount(8) AND U1/uDevideCount(9) AND U1/uDevideCount(16)); FDCPE_Led0: FDCPE port map (Led(0),Led_D(0),NOT Devided_Clk,'0','0'); Led_D(0) <= ((Reset AND Led(7)) OR (NOT Reset AND DipSwitch(0))); FDCPE_Led1: FDCPE port map (Led(1),Led_D(1),NOT Devided_Clk,'0','0'); Led_D(1) <= ((Reset AND Led(0)) OR (NOT Reset AND DipSwitch(1))); FDCPE_Led2: FDCPE port map (Led(2),Led_D(2),NOT Devided_Clk,'0','0'); Led_D(2) <= ((Reset AND Led(1)) OR (NOT Reset AND DipSwitch(2))); FDCPE_Led3: FDCPE port map (Led(3),Led_D(3),NOT Devided_Clk,'0','0'); Led_D(3) <= ((Reset AND Led(2)) OR (NOT Reset AND DipSwitch(3))); FDCPE_Led4: FDCPE port map (Led(4),Led_D(4),NOT Devided_Clk,'0','0'); Led_D(4) <= ((Reset AND Led(3)) OR (NOT Reset AND DipSwitch(4))); FDCPE_Led5: FDCPE port map (Led(5),Led_D(5),NOT Devided_Clk,'0','0'); Led_D(5) <= ((Reset AND Led(4)) OR (NOT Reset AND DipSwitch(5))); FDCPE_Led6: FDCPE port map (Led(6),Led_D(6),NOT Devided_Clk,'0','0'); Led_D(6) <= ((Reset AND Led(5)) OR (NOT Reset AND DipSwitch(6))); FDCPE_Led7: FDCPE port map (Led(7),Led_D(7),NOT Devided_Clk,'0','0'); Led_D(7) <= ((Reset AND Led(6)) OR (NOT Reset AND DipSwitch(7))); FTCPE_U1/uDevideCount0: FTCPE port map (U1/uDevideCount(0),U1/uDevideCount_T(0),Clk,NOT Reset,'0'); U1/uDevideCount_T(0) <= (NOT U1/uDevideCount(0) AND U1/uDevideCount(10) AND NOT U1/uDevideCount(11) AND NOT U1/uDevideCount(12) AND NOT U1/uDevideCount(13) AND NOT U1/uDevideCount(14) AND U1/uDevideCount(15) AND NOT U1/uDevideCount(1) AND NOT U1/uDevideCount(2) AND NOT U1/uDevideCount(3) AND NOT U1/uDevideCount(4) AND U1/uDevideCount(5) AND NOT U1/uDevideCount(6) AND U1/uDevideCount(7) AND NOT U1/uDevideCount(8) AND U1/uDevideCount(9) AND U1/uDevideCount(16)); FTCPE_U1/uDevideCount1: FTCPE port map (U1/uDevideCount(1),U1/uDevideCount(0),Clk,NOT Reset,'0'); FTCPE_U1/uDevideCount2: FTCPE port map (U1/uDevideCount(2),U1/uDevideCount_T(2),Clk,NOT Reset,'0'); U1/uDevideCount_T(2) <= (U1/uDevideCount(0) AND U1/uDevideCount(1)); FTCPE_U1/uDevideCount3: FTCPE port map (U1/uDevideCount(3),U1/uDevideCount_T(3),Clk,NOT Reset,'0'); U1/uDevideCount_T(3) <= (U1/uDevideCount(0) AND U1/uDevideCount(1) AND U1/uDevideCount(2)); FTCPE_U1/uDevideCount4: FTCPE port map (U1/uDevideCount(4),U1/uDevideCount_T(4),Clk,NOT Reset,'0'); U1/uDevideCount_T(4) <= (U1/uDevideCount(0) AND U1/uDevideCount(1) AND U1/uDevideCount(2) AND U1/uDevideCount(3)); FTCPE_U1/uDevideCount5: FTCPE port map (U1/uDevideCount(5),U1/uDevideCount_T(5),Clk,NOT Reset,'0'); U1/uDevideCount_T(5) <= ((U1/uDevideCount(0) AND U1/uDevideCount(1) AND U1/uDevideCount(2) AND U1/uDevideCount(3) AND U1/uDevideCount(4)) OR (NOT U1/uDevideCount(0) AND U1/uDevideCount(10) AND NOT U1/uDevideCount(11) AND NOT U1/uDevideCount(12) AND NOT U1/uDevideCount(13) AND NOT U1/uDevideCount(14) AND U1/uDevideCount(15) AND NOT U1/uDevideCount(1) AND NOT U1/uDevideCount(2) AND NOT U1/uDevideCount(3) AND NOT U1/uDevideCount(4) AND U1/uDevideCount(5) AND NOT U1/uDevideCount(6) AND U1/uDevideCount(7) AND NOT U1/uDevideCount(8) AND U1/uDevideCount(9) AND U1/uDevideCount(16))); FTCPE_U1/uDevideCount6: FTCPE port map (U1/uDevideCount(6),U1/uDevideCount_T(6),Clk,NOT Reset,'0'); U1/uDevideCount_T(6) <= (U1/uDevideCount(0) AND U1/uDevideCount(1) AND U1/uDevideCount(2) AND U1/uDevideCount(3) AND U1/uDevideCount(4) AND U1/uDevideCount(5)); FTCPE_U1/uDevideCount7: FTCPE port map (U1/uDevideCount(7),U1/uDevideCount_T(7),Clk,NOT Reset,'0'); U1/uDevideCount_T(7) <= ((U1/uDevideCount(0) AND U1/uDevideCount(1) AND U1/uDevideCount(2) AND U1/uDevideCount(3) AND U1/uDevideCount(4) AND U1/uDevideCount(5) AND U1/uDevideCount(6)) OR (NOT U1/uDevideCount(0) AND U1/uDevideCount(10) AND NOT U1/uDevideCount(11) AND NOT U1/uDevideCount(12) AND NOT U1/uDevideCount(13) AND NOT U1/uDevideCount(14) AND U1/uDevideCount(15) AND NOT U1/uDevideCount(1) AND NOT U1/uDevideCount(2) AND NOT U1/uDevideCount(3) AND NOT U1/uDevideCount(4) AND U1/uDevideCount(5) AND NOT U1/uDevideCount(6) AND U1/uDevideCount(7) AND NOT U1/uDevideCount(8) AND U1/uDevideCount(9) AND U1/uDevideCount(16))); FTCPE_U1/uDevideCount8: FTCPE port map (U1/uDevideCount(8),U1/uDevideCount_T(8),Clk,NOT Reset,'0'); U1/uDevideCount_T(8) <= (U1/uDevideCount(0) AND U1/uDevideCount(1) AND U1/uDevideCount(2) AND U1/uDevideCount(3) AND U1/uDevideCount(4) AND U1/uDevideCount(5) AND U1/uDevideCount(6) AND U1/uDevideCount(7)); FTCPE_U1/uDevideCount9: FTCPE port map (U1/uDevideCount(9),U1/uDevideCount_T(9),Clk,NOT Reset,'0'); U1/uDevideCount_T(9) <= ((U1/uDevideCount(0) AND U1/uDevideCount(1) AND U1/uDevideCount(2) AND U1/uDevideCount(3) AND U1/uDevideCount(4) AND U1/uDevideCount(5) AND U1/uDevideCount(6) AND U1/uDevideCount(7) AND U1/uDevideCount(8)) OR (NOT U1/uDevideCount(0) AND U1/uDevideCount(10) AND NOT U1/uDevideCount(11) AND NOT U1/uDevideCount(12) AND NOT U1/uDevideCount(13) AND NOT U1/uDevideCount(14) AND U1/uDevideCount(15) AND NOT U1/uDevideCount(1) AND NOT U1/uDevideCount(2) AND NOT U1/uDevideCount(3) AND NOT U1/uDevideCount(4) AND U1/uDevideCount(5) AND NOT U1/uDevideCount(6) AND U1/uDevideCount(7) AND NOT U1/uDevideCount(8) AND U1/uDevideCount(9) AND U1/uDevideCount(16))); FTCPE_U1/uDevideCount10: FTCPE port map (U1/uDevideCount(10),U1/uDevideCount_T(10),Clk,NOT Reset,'0'); U1/uDevideCount_T(10) <= ((U1/uDevideCount(0) AND U1/uDevideCount(1) AND U1/uDevideCount(2) AND U1/uDevideCount(3) AND U1/uDevideCount(4) AND U1/uDevideCount(5) AND U1/uDevideCount(6) AND U1/uDevideCount(7) AND U1/uDevideCount(8) AND U1/uDevideCount(9)) OR (NOT U1/uDevideCount(0) AND U1/uDevideCount(10) AND NOT U1/uDevideCount(11) AND NOT U1/uDevideCount(12) AND NOT U1/uDevideCount(13) AND NOT U1/uDevideCount(14) AND U1/uDevideCount(15) AND NOT U1/uDevideCount(1) AND NOT U1/uDevideCount(2) AND NOT U1/uDevideCount(3) AND NOT U1/uDevideCount(4) AND U1/uDevideCount(5) AND NOT U1/uDevideCount(6) AND U1/uDevideCount(7) AND NOT U1/uDevideCount(8) AND U1/uDevideCount(9) AND U1/uDevideCount(16))); FTCPE_U1/uDevideCount11: FTCPE port map (U1/uDevideCount(11),U1/uDevideCount_T(11),Clk,NOT Reset,'0'); U1/uDevideCount_T(11) <= (U1/uDevideCount(0) AND U1/uDevideCount(10) AND U1/uDevideCount(1) AND U1/uDevideCount(2) AND U1/uDevideCount(3) AND U1/uDevideCount(4) AND U1/uDevideCount(5) AND U1/uDevideCount(6) AND U1/uDevideCount(7) AND U1/uDevideCount(8) AND U1/uDevideCount(9)); FTCPE_U1/uDevideCount12: FTCPE port map (U1/uDevideCount(12),U1/uDevideCount_T(12),Clk,NOT Reset,'0'); U1/uDevideCount_T(12) <= (U1/uDevideCount(0) AND U1/uDevideCount(10) AND U1/uDevideCount(11) AND U1/uDevideCount(1) AND U1/uDevideCount(2) AND U1/uDevideCount(3) AND U1/uDevideCount(4) AND U1/uDevideCount(5) AND U1/uDevideCount(6) AND U1/uDevideCount(7) AND U1/uDevideCount(8) AND U1/uDevideCount(9)); FTCPE_U1/uDevideCount13: FTCPE port map (U1/uDevideCount(13),U1/uDevideCount_T(13),Clk,NOT Reset,'0'); U1/uDevideCount_T(13) <= (U1/uDevideCount(0) AND U1/uDevideCount(10) AND U1/uDevideCount(11) AND U1/uDevideCount(12) AND U1/uDevideCount(1) AND U1/uDevideCount(2) AND U1/uDevideCount(3) AND U1/uDevideCount(4) AND U1/uDevideCount(5) AND U1/uDevideCount(6) AND U1/uDevideCount(7) AND U1/uDevideCount(8) AND U1/uDevideCount(9)); FTCPE_U1/uDevideCount14: FTCPE port map (U1/uDevideCount(14),U1/uDevideCount_T(14),Clk,NOT Reset,'0'); U1/uDevideCount_T(14) <= (U1/uDevideCount(0) AND U1/uDevideCount(10) AND U1/uDevideCount(11) AND U1/uDevideCount(12) AND U1/uDevideCount(13) AND U1/uDevideCount(1) AND U1/uDevideCount(2) AND U1/uDevideCount(3) AND U1/uDevideCount(4) AND U1/uDevideCount(5) AND U1/uDevideCount(6) AND U1/uDevideCount(7) AND U1/uDevideCount(8) AND U1/uDevideCount(9)); FTCPE_U1/uDevideCount15: FTCPE port map (U1/uDevideCount(15),U1/uDevideCount_T(15),Clk,NOT Reset,'0'); U1/uDevideCount_T(15) <= ((U1/uDevideCount(0) AND U1/uDevideCount(10) AND U1/uDevideCount(11) AND U1/uDevideCount(12) AND U1/uDevideCount(13) AND U1/uDevideCount(14) AND U1/uDevideCount(1) AND U1/uDevideCount(2) AND U1/uDevideCount(3) AND U1/uDevideCount(4) AND U1/uDevideCount(5) AND U1/uDevideCount(6) AND U1/uDevideCount(7) AND U1/uDevideCount(8) AND U1/uDevideCount(9)) OR (NOT U1/uDevideCount(0) AND U1/uDevideCount(10) AND NOT U1/uDevideCount(11) AND NOT U1/uDevideCount(12) AND NOT U1/uDevideCount(13) AND NOT U1/uDevideCount(14) AND U1/uDevideCount(15) AND NOT U1/uDevideCount(1) AND NOT U1/uDevideCount(2) AND NOT U1/uDevideCount(3) AND NOT U1/uDevideCount(4) AND U1/uDevideCount(5) AND NOT U1/uDevideCount(6) AND U1/uDevideCount(7) AND NOT U1/uDevideCount(8) AND U1/uDevideCount(9) AND U1/uDevideCount(16))); FTCPE_U1/uDevideCount16: FTCPE port map (U1/uDevideCount(16),U1/uDevideCount_T(16),Clk,NOT Reset,'0'); U1/uDevideCount_T(16) <= ((U1/uDevideCount(0) AND U1/uDevideCount(10) AND U1/uDevideCount(11) AND U1/uDevideCount(12) AND U1/uDevideCount(13) AND U1/uDevideCount(14) AND U1/uDevideCount(15) AND U1/uDevideCount(1) AND U1/uDevideCount(2) AND U1/uDevideCount(3) AND U1/uDevideCount(4) AND U1/uDevideCount(5) AND U1/uDevideCount(6) AND U1/uDevideCount(7) AND U1/uDevideCount(8) AND U1/uDevideCount(9)) OR (NOT U1/uDevideCount(0) AND U1/uDevideCount(10) AND NOT U1/uDevideCount(11) AND NOT U1/uDevideCount(12) AND NOT U1/uDevideCount(13) AND NOT U1/uDevideCount(14) AND U1/uDevideCount(15) AND NOT U1/uDevideCount(1) AND NOT U1/uDevideCount(2) AND NOT U1/uDevideCount(3) AND NOT U1/uDevideCount(4) AND U1/uDevideCount(5) AND NOT U1/uDevideCount(6) AND U1/uDevideCount(7) AND NOT U1/uDevideCount(8) AND U1/uDevideCount(9) AND U1/uDevideCount(16))); Register Legend: FDCPE (Q,D,C,CLR,PRE,CE); FTCPE (Q,D,C,CLR,PRE,CE); LDCP (Q,D,G,CLR,PRE); ****************************** Device Pin Out ***************************** Device : XC9536XL-5-VQ44 -------------------------------- /44 43 42 41 40 39 38 37 36 35 34 \ | 1 33 | | 2 32 | | 3 31 | | 4 30 | | 5 XC9536XL-5-VQ44 29 | | 6 28 | | 7 27 | | 8 26 | | 9 25 | | 10 24 | | 11 23 | \ 12 13 14 15 16 17 18 19 20 21 22 / -------------------------------- Pin Signal Pin Signal No. Name No. Name 1 KPR 23 Led<6> 2 KPR 24 TDO 3 KPR 25 GND 4 GND 26 VCC 5 KPR 27 Led<5> 6 KPR 28 Led<4> 7 KPR 29 Led<3> 8 KPR 30 Led<2> 9 TDI 31 Led<1> 10 TMS 32 Led<0> 11 TCK 33 DipSwitch<6> 12 KPR 34 DipSwitch<5> 13 KPR 35 VCC 14 KPR 36 DipSwitch<4> 15 VCC 37 DipSwitch<3> 16 KPR 38 DipSwitch<2> 17 GND 39 DipSwitch<1> 18 KPR 40 KPR 19 KPR 41 KPR 20 DipSwitch<0> 42 KPR 21 DipSwitch<7> 43 Clk 22 Led<7> 44 Reset Legend : NC = Not Connected, unbonded pin PGND = Unused I/O configured as additional Ground pin TIE = Unused I/O floating -- must tie to VCC, GND or other signal KPR = Unused I/O with weak keeper (leave unconnected) VCC = Dedicated Power Pin GND = Dedicated Ground Pin TDI = Test Data In, JTAG pin TDO = Test Data Out, JTAG pin TCK = Test Clock, JTAG pin TMS = Test Mode Select, JTAG pin PROHIBITED = User reserved pin **************************** Compiler Options **************************** Following is a list of all global compiler options used by the fitter run. Device(s) Specified : xc9536xl-5-VQ44 Optimization Method : SPEED Multi-Level Logic Optimization : ON Ignore Timing Specifications : OFF Default Register Power Up Value : LOW Keep User Location Constraints : ON What-You-See-Is-What-You-Get : OFF Exhaustive Fitting : OFF Keep Unused Inputs : OFF Slew Rate : FAST Power Mode : STD Ground on Unused IOs : OFF Set I/O Pin Termination : KEEPER Global Clock Optimization : ON Global Set/Reset Optimization : ON Global Ouput Enable Optimization : ON Input Limit : 54 Pterm Limit : 25