Timing Report

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Design Name BoardTest
Device, Speed (SpeedFile Version) XC9536XL, -5 (3.0)
Date Created Thu Jul 10 00:05:05 2008
Created By Timing Report Generator: version K.37
Copyright Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved.

Summary

Notes and Warnings
Note: This design contains no timing constraints.
Note: A default set of constraints using a delay of 0.000ns will be used for analysis.

Performance Summary
Min. Clock Period 10.000 ns.
Max. Clock Frequency (fSYSTEM) 100.000 MHz.
Limited by Clock Pulse Width for Devided_Clk.Q
Clock to Setup (tCYC) 5.600 ns.
Setup to Clock at the Pad (tSU) 0.900 ns.
Clock Pad to Output Pad Delay (tCO) 7.400 ns.

Timing Constraints

Constraint Name Requirement (ns) Delay (ns) Paths Paths Failing
TS1000 0.0 0.0 0 0
TS1001 0.0 0.0 0 0
AUTO_TS_F2F 0.0 5.6 218 218
AUTO_TS_P2P 0.0 7.4 8 8
AUTO_TS_P2F 0.0 4.8 17 17
AUTO_TS_F2P 0.0 2.4 8 8


Constraint: TS1000

Description: PERIOD:PERIOD_Devided_Clk.Q:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1001

Description: PERIOD:PERIOD_Clk:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: AUTO_TS_F2F

Description: MAXDELAY:FROM:FFS(*):TO:FFS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
Led<0>.Q to Led<1>.D 0.000 5.600 -5.600
Led<1>.Q to Led<2>.D 0.000 5.600 -5.600
Led<2>.Q to Led<3>.D 0.000 5.600 -5.600


Constraint: AUTO_TS_P2P

Description: MAXDELAY:FROM:PADS(*):TO:PADS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
Clk to Led<0> 0.000 7.400 -7.400
Clk to Led<1> 0.000 7.400 -7.400
Clk to Led<2> 0.000 7.400 -7.400


Constraint: AUTO_TS_P2F

Description: MAXDELAY:FROM:PADS(*):TO:FFS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
DipSwitch<0> to Led<0>.D 0.000 4.800 -4.800
DipSwitch<1> to Led<1>.D 0.000 4.800 -4.800
DipSwitch<2> to Led<2>.D 0.000 4.800 -4.800


Constraint: AUTO_TS_F2P

Description: MAXDELAY:FROM:FFS(*):TO:PADS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
Led<0>.Q to Led<0> 0.000 2.400 -2.400
Led<1>.Q to Led<1> 0.000 2.400 -2.400
Led<2>.Q to Led<2> 0.000 2.400 -2.400



Number of constraints not met: 4

Data Sheet Report

Maximum External Clock Speeds

Clock fEXT (MHz) Reason
Devided_Clk.Q 100.000 Limited by Clock Pulse Width for Devided_Clk.Q
Clk 178.571 Limited by Clock Pulse Width for Clk

Setup/Hold Times for Clocks

Setup/Hold Times for Clock Devided_Clk.Q
Source Pad Setup to clk (edge) Hold to clk (edge)
DipSwitch<0> 0.900 0.500
DipSwitch<1> 0.900 0.500
DipSwitch<2> 0.900 0.500
DipSwitch<3> 0.900 0.500
DipSwitch<4> 0.900 0.500
DipSwitch<5> 0.900 0.500
DipSwitch<6> 0.900 0.500
DipSwitch<7> 0.900 0.500
Reset 0.900 0.500


Clock to Pad Timing

Clock Clk to Pad
Destination Pad Clock (edge) to Pad
Led<0> 7.400
Led<1> 7.400
Led<2> 7.400
Led<3> 7.400
Led<4> 7.400
Led<5> 7.400
Led<6> 7.400
Led<7> 7.400


Clock to Setup Times for Clocks

Clock to Setup for clock Devided_Clk.Q
Source Destination Delay
Led<0>.Q Led<1>.D 5.600
Led<1>.Q Led<2>.D 5.600
Led<2>.Q Led<3>.D 5.600
Led<3>.Q Led<4>.D 5.600
Led<4>.Q Led<5>.D 5.600
Led<5>.Q Led<6>.D 5.600
Led<6>.Q Led<7>.D 5.600
Led<7>.Q Led<0>.D 5.600

Clock to Setup for clock Clk
Source Destination Delay
U1/uDevideCount<0>.Q Devided_Clk.CE 5.600
U1/uDevideCount<0>.Q U1/uDevideCount<0>.D 5.600
U1/uDevideCount<0>.Q U1/uDevideCount<10>.D 5.600
U1/uDevideCount<0>.Q U1/uDevideCount<11>.D 5.600
U1/uDevideCount<0>.Q U1/uDevideCount<12>.D 5.600
U1/uDevideCount<0>.Q U1/uDevideCount<13>.D 5.600
U1/uDevideCount<0>.Q U1/uDevideCount<14>.D 5.600
U1/uDevideCount<0>.Q U1/uDevideCount<15>.D 5.600
U1/uDevideCount<0>.Q U1/uDevideCount<16>.D 5.600
U1/uDevideCount<0>.Q U1/uDevideCount<1>.D 5.600
U1/uDevideCount<0>.Q U1/uDevideCount<2>.D 5.600
U1/uDevideCount<0>.Q U1/uDevideCount<3>.D 5.600
U1/uDevideCount<0>.Q U1/uDevideCount<4>.D 5.600
U1/uDevideCount<0>.Q U1/uDevideCount<5>.D 5.600
U1/uDevideCount<0>.Q U1/uDevideCount<6>.D 5.600
U1/uDevideCount<0>.Q U1/uDevideCount<7>.D 5.600
U1/uDevideCount<0>.Q U1/uDevideCount<8>.D 5.600
U1/uDevideCount<0>.Q U1/uDevideCount<9>.D 5.600
U1/uDevideCount<10>.Q Devided_Clk.CE 5.600
U1/uDevideCount<10>.Q U1/uDevideCount<0>.D 5.600
U1/uDevideCount<10>.Q U1/uDevideCount<10>.D 5.600
U1/uDevideCount<10>.Q U1/uDevideCount<11>.D 5.600
U1/uDevideCount<10>.Q U1/uDevideCount<12>.D 5.600
U1/uDevideCount<10>.Q U1/uDevideCount<13>.D 5.600
U1/uDevideCount<10>.Q U1/uDevideCount<14>.D 5.600
U1/uDevideCount<10>.Q U1/uDevideCount<15>.D 5.600
U1/uDevideCount<10>.Q U1/uDevideCount<16>.D 5.600
U1/uDevideCount<10>.Q U1/uDevideCount<5>.D 5.600
U1/uDevideCount<10>.Q U1/uDevideCount<7>.D 5.600
U1/uDevideCount<10>.Q U1/uDevideCount<9>.D 5.600
U1/uDevideCount<11>.Q Devided_Clk.CE 5.600
U1/uDevideCount<11>.Q U1/uDevideCount<0>.D 5.600
U1/uDevideCount<11>.Q U1/uDevideCount<10>.D 5.600
U1/uDevideCount<11>.Q U1/uDevideCount<12>.D 5.600
U1/uDevideCount<11>.Q U1/uDevideCount<13>.D 5.600
U1/uDevideCount<11>.Q U1/uDevideCount<14>.D 5.600
U1/uDevideCount<11>.Q U1/uDevideCount<15>.D 5.600
U1/uDevideCount<11>.Q U1/uDevideCount<16>.D 5.600
U1/uDevideCount<11>.Q U1/uDevideCount<5>.D 5.600
U1/uDevideCount<11>.Q U1/uDevideCount<7>.D 5.600
U1/uDevideCount<11>.Q U1/uDevideCount<9>.D 5.600
U1/uDevideCount<12>.Q Devided_Clk.CE 5.600
U1/uDevideCount<12>.Q U1/uDevideCount<0>.D 5.600
U1/uDevideCount<12>.Q U1/uDevideCount<10>.D 5.600
U1/uDevideCount<12>.Q U1/uDevideCount<13>.D 5.600
U1/uDevideCount<12>.Q U1/uDevideCount<14>.D 5.600
U1/uDevideCount<12>.Q U1/uDevideCount<15>.D 5.600
U1/uDevideCount<12>.Q U1/uDevideCount<16>.D 5.600
U1/uDevideCount<12>.Q U1/uDevideCount<5>.D 5.600
U1/uDevideCount<12>.Q U1/uDevideCount<7>.D 5.600
U1/uDevideCount<12>.Q U1/uDevideCount<9>.D 5.600
U1/uDevideCount<13>.Q Devided_Clk.CE 5.600
U1/uDevideCount<13>.Q U1/uDevideCount<0>.D 5.600
U1/uDevideCount<13>.Q U1/uDevideCount<10>.D 5.600
U1/uDevideCount<13>.Q U1/uDevideCount<14>.D 5.600
U1/uDevideCount<13>.Q U1/uDevideCount<15>.D 5.600
U1/uDevideCount<13>.Q U1/uDevideCount<16>.D 5.600
U1/uDevideCount<13>.Q U1/uDevideCount<5>.D 5.600
U1/uDevideCount<13>.Q U1/uDevideCount<7>.D 5.600
U1/uDevideCount<13>.Q U1/uDevideCount<9>.D 5.600
U1/uDevideCount<14>.Q Devided_Clk.CE 5.600
U1/uDevideCount<14>.Q U1/uDevideCount<0>.D 5.600
U1/uDevideCount<14>.Q U1/uDevideCount<10>.D 5.600
U1/uDevideCount<14>.Q U1/uDevideCount<15>.D 5.600
U1/uDevideCount<14>.Q U1/uDevideCount<16>.D 5.600
U1/uDevideCount<14>.Q U1/uDevideCount<5>.D 5.600
U1/uDevideCount<14>.Q U1/uDevideCount<7>.D 5.600
U1/uDevideCount<14>.Q U1/uDevideCount<9>.D 5.600
U1/uDevideCount<15>.Q Devided_Clk.CE 5.600
U1/uDevideCount<15>.Q U1/uDevideCount<0>.D 5.600
U1/uDevideCount<15>.Q U1/uDevideCount<10>.D 5.600
U1/uDevideCount<15>.Q U1/uDevideCount<15>.D 5.600
U1/uDevideCount<15>.Q U1/uDevideCount<16>.D 5.600
U1/uDevideCount<15>.Q U1/uDevideCount<5>.D 5.600
U1/uDevideCount<15>.Q U1/uDevideCount<7>.D 5.600
U1/uDevideCount<15>.Q U1/uDevideCount<9>.D 5.600
U1/uDevideCount<16>.Q Devided_Clk.CE 5.600
U1/uDevideCount<16>.Q U1/uDevideCount<0>.D 5.600
U1/uDevideCount<16>.Q U1/uDevideCount<10>.D 5.600
U1/uDevideCount<16>.Q U1/uDevideCount<15>.D 5.600
U1/uDevideCount<16>.Q U1/uDevideCount<16>.D 5.600
U1/uDevideCount<16>.Q U1/uDevideCount<5>.D 5.600
U1/uDevideCount<16>.Q U1/uDevideCount<7>.D 5.600
U1/uDevideCount<16>.Q U1/uDevideCount<9>.D 5.600
U1/uDevideCount<1>.Q Devided_Clk.CE 5.600
U1/uDevideCount<1>.Q U1/uDevideCount<0>.D 5.600
U1/uDevideCount<1>.Q U1/uDevideCount<10>.D 5.600
U1/uDevideCount<1>.Q U1/uDevideCount<11>.D 5.600
U1/uDevideCount<1>.Q U1/uDevideCount<12>.D 5.600
U1/uDevideCount<1>.Q U1/uDevideCount<13>.D 5.600
U1/uDevideCount<1>.Q U1/uDevideCount<14>.D 5.600
U1/uDevideCount<1>.Q U1/uDevideCount<15>.D 5.600
U1/uDevideCount<1>.Q U1/uDevideCount<16>.D 5.600
U1/uDevideCount<1>.Q U1/uDevideCount<2>.D 5.600
U1/uDevideCount<1>.Q U1/uDevideCount<3>.D 5.600
U1/uDevideCount<1>.Q U1/uDevideCount<4>.D 5.600
U1/uDevideCount<1>.Q U1/uDevideCount<5>.D 5.600
U1/uDevideCount<1>.Q U1/uDevideCount<6>.D 5.600
U1/uDevideCount<1>.Q U1/uDevideCount<7>.D 5.600
U1/uDevideCount<1>.Q U1/uDevideCount<8>.D 5.600
U1/uDevideCount<1>.Q U1/uDevideCount<9>.D 5.600
U1/uDevideCount<2>.Q Devided_Clk.CE 5.600
U1/uDevideCount<2>.Q U1/uDevideCount<0>.D 5.600
U1/uDevideCount<2>.Q U1/uDevideCount<10>.D 5.600
U1/uDevideCount<2>.Q U1/uDevideCount<11>.D 5.600
U1/uDevideCount<2>.Q U1/uDevideCount<12>.D 5.600
U1/uDevideCount<2>.Q U1/uDevideCount<13>.D 5.600
U1/uDevideCount<2>.Q U1/uDevideCount<14>.D 5.600
U1/uDevideCount<2>.Q U1/uDevideCount<15>.D 5.600
U1/uDevideCount<2>.Q U1/uDevideCount<16>.D 5.600
U1/uDevideCount<2>.Q U1/uDevideCount<3>.D 5.600
U1/uDevideCount<2>.Q U1/uDevideCount<4>.D 5.600
U1/uDevideCount<2>.Q U1/uDevideCount<5>.D 5.600
U1/uDevideCount<2>.Q U1/uDevideCount<6>.D 5.600
U1/uDevideCount<2>.Q U1/uDevideCount<7>.D 5.600
U1/uDevideCount<2>.Q U1/uDevideCount<8>.D 5.600
U1/uDevideCount<2>.Q U1/uDevideCount<9>.D 5.600
U1/uDevideCount<3>.Q Devided_Clk.CE 5.600
U1/uDevideCount<3>.Q U1/uDevideCount<0>.D 5.600
U1/uDevideCount<3>.Q U1/uDevideCount<10>.D 5.600
U1/uDevideCount<3>.Q U1/uDevideCount<11>.D 5.600
U1/uDevideCount<3>.Q U1/uDevideCount<12>.D 5.600
U1/uDevideCount<3>.Q U1/uDevideCount<13>.D 5.600
U1/uDevideCount<3>.Q U1/uDevideCount<14>.D 5.600
U1/uDevideCount<3>.Q U1/uDevideCount<15>.D 5.600
U1/uDevideCount<3>.Q U1/uDevideCount<16>.D 5.600
U1/uDevideCount<3>.Q U1/uDevideCount<4>.D 5.600
U1/uDevideCount<3>.Q U1/uDevideCount<5>.D 5.600
U1/uDevideCount<3>.Q U1/uDevideCount<6>.D 5.600
U1/uDevideCount<3>.Q U1/uDevideCount<7>.D 5.600
U1/uDevideCount<3>.Q U1/uDevideCount<8>.D 5.600
U1/uDevideCount<3>.Q U1/uDevideCount<9>.D 5.600
U1/uDevideCount<4>.Q Devided_Clk.CE 5.600
U1/uDevideCount<4>.Q U1/uDevideCount<0>.D 5.600
U1/uDevideCount<4>.Q U1/uDevideCount<10>.D 5.600
U1/uDevideCount<4>.Q U1/uDevideCount<11>.D 5.600
U1/uDevideCount<4>.Q U1/uDevideCount<12>.D 5.600
U1/uDevideCount<4>.Q U1/uDevideCount<13>.D 5.600
U1/uDevideCount<4>.Q U1/uDevideCount<14>.D 5.600
U1/uDevideCount<4>.Q U1/uDevideCount<15>.D 5.600
U1/uDevideCount<4>.Q U1/uDevideCount<16>.D 5.600
U1/uDevideCount<4>.Q U1/uDevideCount<5>.D 5.600
U1/uDevideCount<4>.Q U1/uDevideCount<6>.D 5.600
U1/uDevideCount<4>.Q U1/uDevideCount<7>.D 5.600
U1/uDevideCount<4>.Q U1/uDevideCount<8>.D 5.600
U1/uDevideCount<4>.Q U1/uDevideCount<9>.D 5.600
U1/uDevideCount<5>.Q Devided_Clk.CE 5.600
U1/uDevideCount<5>.Q U1/uDevideCount<0>.D 5.600
U1/uDevideCount<5>.Q U1/uDevideCount<10>.D 5.600
U1/uDevideCount<5>.Q U1/uDevideCount<11>.D 5.600
U1/uDevideCount<5>.Q U1/uDevideCount<12>.D 5.600
U1/uDevideCount<5>.Q U1/uDevideCount<13>.D 5.600
U1/uDevideCount<5>.Q U1/uDevideCount<14>.D 5.600
U1/uDevideCount<5>.Q U1/uDevideCount<15>.D 5.600
U1/uDevideCount<5>.Q U1/uDevideCount<16>.D 5.600
U1/uDevideCount<5>.Q U1/uDevideCount<5>.D 5.600
U1/uDevideCount<5>.Q U1/uDevideCount<6>.D 5.600
U1/uDevideCount<5>.Q U1/uDevideCount<7>.D 5.600
U1/uDevideCount<5>.Q U1/uDevideCount<8>.D 5.600
U1/uDevideCount<5>.Q U1/uDevideCount<9>.D 5.600
U1/uDevideCount<6>.Q Devided_Clk.CE 5.600
U1/uDevideCount<6>.Q U1/uDevideCount<0>.D 5.600
U1/uDevideCount<6>.Q U1/uDevideCount<10>.D 5.600
U1/uDevideCount<6>.Q U1/uDevideCount<11>.D 5.600
U1/uDevideCount<6>.Q U1/uDevideCount<12>.D 5.600
U1/uDevideCount<6>.Q U1/uDevideCount<13>.D 5.600
U1/uDevideCount<6>.Q U1/uDevideCount<14>.D 5.600
U1/uDevideCount<6>.Q U1/uDevideCount<15>.D 5.600
U1/uDevideCount<6>.Q U1/uDevideCount<16>.D 5.600
U1/uDevideCount<6>.Q U1/uDevideCount<5>.D 5.600
U1/uDevideCount<6>.Q U1/uDevideCount<7>.D 5.600
U1/uDevideCount<6>.Q U1/uDevideCount<8>.D 5.600
U1/uDevideCount<6>.Q U1/uDevideCount<9>.D 5.600
U1/uDevideCount<7>.Q Devided_Clk.CE 5.600
U1/uDevideCount<7>.Q U1/uDevideCount<0>.D 5.600
U1/uDevideCount<7>.Q U1/uDevideCount<10>.D 5.600
U1/uDevideCount<7>.Q U1/uDevideCount<11>.D 5.600
U1/uDevideCount<7>.Q U1/uDevideCount<12>.D 5.600
U1/uDevideCount<7>.Q U1/uDevideCount<13>.D 5.600
U1/uDevideCount<7>.Q U1/uDevideCount<14>.D 5.600
U1/uDevideCount<7>.Q U1/uDevideCount<15>.D 5.600
U1/uDevideCount<7>.Q U1/uDevideCount<16>.D 5.600
U1/uDevideCount<7>.Q U1/uDevideCount<5>.D 5.600
U1/uDevideCount<7>.Q U1/uDevideCount<7>.D 5.600
U1/uDevideCount<7>.Q U1/uDevideCount<8>.D 5.600
U1/uDevideCount<7>.Q U1/uDevideCount<9>.D 5.600
U1/uDevideCount<8>.Q Devided_Clk.CE 5.600
U1/uDevideCount<8>.Q U1/uDevideCount<0>.D 5.600
U1/uDevideCount<8>.Q U1/uDevideCount<10>.D 5.600
U1/uDevideCount<8>.Q U1/uDevideCount<11>.D 5.600
U1/uDevideCount<8>.Q U1/uDevideCount<12>.D 5.600
U1/uDevideCount<8>.Q U1/uDevideCount<13>.D 5.600
U1/uDevideCount<8>.Q U1/uDevideCount<14>.D 5.600
U1/uDevideCount<8>.Q U1/uDevideCount<15>.D 5.600
U1/uDevideCount<8>.Q U1/uDevideCount<16>.D 5.600
U1/uDevideCount<8>.Q U1/uDevideCount<5>.D 5.600
U1/uDevideCount<8>.Q U1/uDevideCount<7>.D 5.600
U1/uDevideCount<8>.Q U1/uDevideCount<9>.D 5.600
U1/uDevideCount<9>.Q Devided_Clk.CE 5.600
U1/uDevideCount<9>.Q U1/uDevideCount<0>.D 5.600
U1/uDevideCount<9>.Q U1/uDevideCount<10>.D 5.600
U1/uDevideCount<9>.Q U1/uDevideCount<11>.D 5.600
U1/uDevideCount<9>.Q U1/uDevideCount<12>.D 5.600
U1/uDevideCount<9>.Q U1/uDevideCount<13>.D 5.600
U1/uDevideCount<9>.Q U1/uDevideCount<14>.D 5.600
U1/uDevideCount<9>.Q U1/uDevideCount<15>.D 5.600
U1/uDevideCount<9>.Q U1/uDevideCount<16>.D 5.600
U1/uDevideCount<9>.Q U1/uDevideCount<5>.D 5.600
U1/uDevideCount<9>.Q U1/uDevideCount<7>.D 5.600
U1/uDevideCount<9>.Q U1/uDevideCount<9>.D 5.600


Pad to Pad List

Source Pad Destination Pad Delay



Number of paths analyzed: 251
Number of Timing errors: 251
Analysis Completed: Thu Jul 10 00:05:05 2008