Triple Data Encryption Standard Peripheral

TDES (AT91S_TDES) 0xFFFA8000 (AT91C_BASE_TDES)
Periph ID AICSymbolDescription
19 (AT91C_ID_TDES)Triple Data Encryption Standard

FunctionDescription
AT91F_TDES_CfgPMCEnable Peripheral clock in PMC for TDES


TDES Software API (AT91S_TDES)

OffsetFieldDescription
0x0TDES_CRControl Register
0x4TDES_MRMode Register
0x10TDES_IERInterrupt Enable Register
0x14TDES_IDRInterrupt Disable Register
0x18TDES_IMRInterrupt Mask Register
0x1CTDES_ISRInterrupt Status Register
0x20TDES_KEY1WxR[2] (TDES_KEY1WxR)Key 1 Word x Register
0x28TDES_KEY2WxR[2] (TDES_KEY2WxR)Key 2 Word x Register
0x30TDES_KEY3WxR[2] (TDES_KEY3WxR)Key 3 Word x Register
0x40TDES_IDATAxR[2] (TDES_IDATAxR)Input Data x Register
0x50TDES_ODATAxR[2] (TDES_ODATAxR)Output Data x Register
0x60TDES_IVxR[2] (TDES_IVxR)Initialization Vector x Register
0xFCTDES_VRTDES Version Register
0x100TDES_RPR (PDC_RPR)Receive Pointer Register
0x104TDES_RCR (PDC_RCR)Receive Counter Register
0x108TDES_TPR (PDC_TPR)Transmit Pointer Register
0x10CTDES_TCR (PDC_TCR)Transmit Counter Register
0x110TDES_RNPR (PDC_RNPR)Receive Next Pointer Register
0x114TDES_RNCR (PDC_RNCR)Receive Next Counter Register
0x118TDES_TNPR (PDC_TNPR)Transmit Next Pointer Register
0x11CTDES_TNCR (PDC_TNCR)Transmit Next Counter Register
0x120TDES_PTCR (PDC_PTCR)PDC Transfer Control Register
0x124TDES_PTSR (PDC_PTSR)PDC Transfer Status Register

FunctionDescription
AT91F_TDES_IsInterruptMaskedTest if TDES Interrupt is Masked
AT91F_TDES_EnableItEnable TDES interrupt
AT91F_TDES_SetInitializationVectorSet Initialization Vector x
AT91F_TDES_SoftResetReset TDES
AT91F_TDES_GetInterruptMaskStatusReturn TDES Interrupt Mask Status
AT91F_TDES_GetModeRegReturn the Mode Register of the TDES controller value
AT91F_TDES_GetOutputDataGet Output Data x
AT91F_TDES_InputDataSet Input Data x
AT91F_TDES_SetCryptoKey1Set Cryptographic Key 1 Word x
AT91F_TDES_SetCryptoKey2Set Cryptographic Key 2 Word x
AT91F_TDES_SetCryptoKey3Set Cryptographic Key 3 Word x
AT91F_TDES_StartProcessingStart Encryption or Decryption
AT91F_TDES_IsStatusSetTest if TDES Status is Set
AT91F_TDES_CfgModeRegConfigure the Mode Register of the TDES controller
AT91F_TDES_DisableItDisable TDES interrupt
AT91F_TDES_GetStatusReturn TDES Interrupt Status

TDES Register Description

TDES: AT91_REG TDES_CR Control Register

OffsetNameDescription
0TDES_START
AT91C_TDES_START
Starts Processing
0 = No effect.
1 = Start Encryption/Decryption process.
8TDES_SWRST
AT91C_TDES_SWRST
Software Reset
0 = No effect.
1 = Resets the TDES. A software triggered hardware reset of the TDES interface is performed.

TDES: AT91_REG TDES_MR Mode Register

OffsetNameDescription
0TDES_CIPHER
AT91C_TDES_CIPHER
Processing Mode
0 = Decrypts Data.
1 = Encrypts Data.
1TDES_TDESMOD
AT91C_TDES_TDESMOD
Single or Triple DES Mode
0: Single DES processing using TDES_KEY1WxR registers.
1: Triple DES processing using TDES_KEY1WxR, TDES_KEY2WxR and TDES_KEY3WxR registers.
4TDES_KEYMOD
AT91C_TDES_KEYMOD
Key Mode
0: Three-key algorithm is selected.
1: Two-key algorithm is selected. There is no need to write TDES_KEY3WxR registers.
9..8TDES_SMOD
AT91C_TDES_SMOD
Start Mode
ValueLabelDescription
0TDES_SMOD_MANUAL
AT91C_TDES_SMOD_MANUAL

Manual Mode: The START bit in register TDES_CR must be set to begin encryption or decryption.
1TDES_SMOD_AUTO
AT91C_TDES_SMOD_AUTO

Auto Mode: no action in TDES_CR is necessary (cf datasheet).
2TDES_SMOD_PDC
AT91C_TDES_SMOD_PDC

PDC Mode (cf datasheet).
13..12TDES_OPMOD
AT91C_TDES_OPMOD
Operation Mode
ValueLabelDescription
0TDES_OPMOD_ECB
AT91C_TDES_OPMOD_ECB

ECB Electronic CodeBook mode.
1TDES_OPMOD_CBC
AT91C_TDES_OPMOD_CBC

CBC Cipher Block Chaining mode.
2TDES_OPMOD_OFB
AT91C_TDES_OPMOD_OFB

OFB Output Feedback mode.
3TDES_OPMOD_CFB
AT91C_TDES_OPMOD_CFB

CFB Cipher Feedback mode.
15TDES_LOD
AT91C_TDES_LOD
Last Output Data Mode
0 = No effect. In Manual and Auto modes, the DATRDY flag is cleared when at least one of the Output Data registers is read.
1 = The DATRDY flag is cleared when at least one of the Input Data Registers is written. No more Output Data Register reads is necessary between consecutive encryptions/decryptions.
17..16TDES_CFBS
AT91C_TDES_CFBS
Cipher Feedback Data Size
ValueLabelDescription
0TDES_CFBS_64_BIT
AT91C_TDES_CFBS_64_BIT

64-bit.
1TDES_CFBS_32_BIT
AT91C_TDES_CFBS_32_BIT

32-bit.
2TDES_CFBS_16_BIT
AT91C_TDES_CFBS_16_BIT

16-bit.
3TDES_CFBS_8_BIT
AT91C_TDES_CFBS_8_BIT

8-bit.

TDES: AT91_REG TDES_IER Interrupt Enable Register

OffsetNameDescription
0TDES_DATRDY
AT91C_TDES_DATRDY
DATRDY
0 = No effect.
1 = En/Dis/Mask/Status of DATRDY (for Manual and Auto Mode in TDES_MR).
1TDES_ENDRX
AT91C_TDES_ENDRX
PDC Read Buffer End
0 = The Receive Counter Register has not reached 0 since the last write in TDES_RCR or TDES_RNCR.
1 = The Receive Counter Register has reached 0 since the last write in TDES_RCR or TDES_RNCR.
2TDES_ENDTX
AT91C_TDES_ENDTX
PDC Write Buffer End
0 = The Transmit Counter Register has not reached 0 since the last write in TDES_TCR or TDES_TNCR.
1 = The Transmit Counter Register has reached 0 since the last write in TDES_TCR or TDES_TNCR.
3TDES_RXBUFF
AT91C_TDES_RXBUFF
PDC Read Buffer Full
0 = TDES_RCR or TDES_RNCR has a value other than 0.
1 = Both TDES_RCR and TDES_RNCR has a value of 0.
4TDES_TXBUFE
AT91C_TDES_TXBUFE
PDC Write Buffer Empty
0 = TDES_TCR or TDES_TNCR has a value other than 0.
1 = Both TDES_TCR and TDES_TNCR has a value of 0.
8TDES_URAD
AT91C_TDES_URAD
Unspecified Register Access Detection
0 = No unspecified register access has been detected since the last SWRST.
1 = At least one unspecified register access has been detected since the last SWRST.

TDES: AT91_REG TDES_IDR Interrupt Disable Register

OffsetNameDescription
0TDES_DATRDY
AT91C_TDES_DATRDY
DATRDY
0 = No effect.
1 = En/Dis/Mask/Status of DATRDY (for Manual and Auto Mode in TDES_MR).
1TDES_ENDRX
AT91C_TDES_ENDRX
PDC Read Buffer End
0 = The Receive Counter Register has not reached 0 since the last write in TDES_RCR or TDES_RNCR.
1 = The Receive Counter Register has reached 0 since the last write in TDES_RCR or TDES_RNCR.
2TDES_ENDTX
AT91C_TDES_ENDTX
PDC Write Buffer End
0 = The Transmit Counter Register has not reached 0 since the last write in TDES_TCR or TDES_TNCR.
1 = The Transmit Counter Register has reached 0 since the last write in TDES_TCR or TDES_TNCR.
3TDES_RXBUFF
AT91C_TDES_RXBUFF
PDC Read Buffer Full
0 = TDES_RCR or TDES_RNCR has a value other than 0.
1 = Both TDES_RCR and TDES_RNCR has a value of 0.
4TDES_TXBUFE
AT91C_TDES_TXBUFE
PDC Write Buffer Empty
0 = TDES_TCR or TDES_TNCR has a value other than 0.
1 = Both TDES_TCR and TDES_TNCR has a value of 0.
8TDES_URAD
AT91C_TDES_URAD
Unspecified Register Access Detection
0 = No unspecified register access has been detected since the last SWRST.
1 = At least one unspecified register access has been detected since the last SWRST.

TDES: AT91_REG TDES_IMR Interrupt Mask Register

OffsetNameDescription
0TDES_DATRDY
AT91C_TDES_DATRDY
DATRDY
0 = No effect.
1 = En/Dis/Mask/Status of DATRDY (for Manual and Auto Mode in TDES_MR).
1TDES_ENDRX
AT91C_TDES_ENDRX
PDC Read Buffer End
0 = The Receive Counter Register has not reached 0 since the last write in TDES_RCR or TDES_RNCR.
1 = The Receive Counter Register has reached 0 since the last write in TDES_RCR or TDES_RNCR.
2TDES_ENDTX
AT91C_TDES_ENDTX
PDC Write Buffer End
0 = The Transmit Counter Register has not reached 0 since the last write in TDES_TCR or TDES_TNCR.
1 = The Transmit Counter Register has reached 0 since the last write in TDES_TCR or TDES_TNCR.
3TDES_RXBUFF
AT91C_TDES_RXBUFF
PDC Read Buffer Full
0 = TDES_RCR or TDES_RNCR has a value other than 0.
1 = Both TDES_RCR and TDES_RNCR has a value of 0.
4TDES_TXBUFE
AT91C_TDES_TXBUFE
PDC Write Buffer Empty
0 = TDES_TCR or TDES_TNCR has a value other than 0.
1 = Both TDES_TCR and TDES_TNCR has a value of 0.
8TDES_URAD
AT91C_TDES_URAD
Unspecified Register Access Detection
0 = No unspecified register access has been detected since the last SWRST.
1 = At least one unspecified register access has been detected since the last SWRST.

TDES: AT91_REG TDES_ISR Interrupt Status Register

OffsetNameDescription
0TDES_DATRDY
AT91C_TDES_DATRDY
DATRDY
0 = No effect.
1 = En/Dis/Mask/Status of DATRDY (for Manual and Auto Mode in TDES_MR).
1TDES_ENDRX
AT91C_TDES_ENDRX
PDC Read Buffer End
0 = The Receive Counter Register has not reached 0 since the last write in TDES_RCR or TDES_RNCR.
1 = The Receive Counter Register has reached 0 since the last write in TDES_RCR or TDES_RNCR.
2TDES_ENDTX
AT91C_TDES_ENDTX
PDC Write Buffer End
0 = The Transmit Counter Register has not reached 0 since the last write in TDES_TCR or TDES_TNCR.
1 = The Transmit Counter Register has reached 0 since the last write in TDES_TCR or TDES_TNCR.
3TDES_RXBUFF
AT91C_TDES_RXBUFF
PDC Read Buffer Full
0 = TDES_RCR or TDES_RNCR has a value other than 0.
1 = Both TDES_RCR and TDES_RNCR has a value of 0.
4TDES_TXBUFE
AT91C_TDES_TXBUFE
PDC Write Buffer Empty
0 = TDES_TCR or TDES_TNCR has a value other than 0.
1 = Both TDES_TCR and TDES_TNCR has a value of 0.
8TDES_URAD
AT91C_TDES_URAD
Unspecified Register Access Detection
0 = No unspecified register access has been detected since the last SWRST.
1 = At least one unspecified register access has been detected since the last SWRST.
13..12TDES_URAT
AT91C_TDES_URAT
Unspecified Register Access Type Status
Only the last Unspecified Register Access Type is available through the URAT field.
ValueLabelDescription
0TDES_URAT_IN_DAT_WRITE_DATPROC
AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC

Input data register written during the data processing in PDC mode.
1TDES_URAT_OUT_DAT_READ_DATPROC
AT91C_TDES_URAT_OUT_DAT_READ_DATPROC

Output data register read during the data processing.
2TDES_URAT_MODEREG_WRITE_DATPROC
AT91C_TDES_URAT_MODEREG_WRITE_DATPROC

Mode register written during the data processing.
3TDES_URAT_WO_REG_READ
AT91C_TDES_URAT_WO_REG_READ

Write-only register read access.

TDES: AT91_REG TDES_KEY1WxR Key 1 Word x Register


Key 1 Word x: The two 32-bit Key 1 Word Registers allow to set the 64-bit cryptographic key used for encryption/decryption.

TDES: AT91_REG TDES_KEY2WxR Key 2 Word x Register


Key 2 Word x: The two 32-bit Key 2 Word Registers allow to set the 64-bit cryptographic key used for encryption/decryption.

TDES: AT91_REG TDES_KEY3WxR Key 3 Word x Register


Key 3 Word x: The two 32-bit Key 3 Word Registers allow to set the 64-bit cryptographic key used for encryption/decryption.

TDES: AT91_REG TDES_IDATAxR Input Data x Register


The two 32-bit Input Data registers allow to set the 64-bit data block used for encryption/decryption.

TDES: AT91_REG TDES_ODATAxR Output Data x Register


The two 32-bit Output Data registers contain the 64-bit data block which has been encrypted/decrypted.

TDES: AT91_REG TDES_IVxR Initialization Vector x Register


The two 32-bit Initialization Vector registers allow to set the 64-bit Initialization Vector data block, which is used by some modes of operation as an additional initial input.

TDES: AT91_REG TDES_VR TDES Version Register

TDES: AT91S_PDC TDES_PDC PDC interface