Periph ID AIC | Symbol | Description |
---|---|---|
19 | (AT91C_ID_TDES) | Triple Data Encryption Standard |
Function | Description |
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AT91F_TDES_CfgPMC | Enable Peripheral clock in PMC for TDES |
Offset | Field | Description |
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0x0 | TDES_CR | Control Register |
0x4 | TDES_MR | Mode Register |
0x10 | TDES_IER | Interrupt Enable Register |
0x14 | TDES_IDR | Interrupt Disable Register |
0x18 | TDES_IMR | Interrupt Mask Register |
0x1C | TDES_ISR | Interrupt Status Register |
0x20 | TDES_KEY1WxR[2] (TDES_KEY1WxR) | Key 1 Word x Register |
0x28 | TDES_KEY2WxR[2] (TDES_KEY2WxR) | Key 2 Word x Register |
0x30 | TDES_KEY3WxR[2] (TDES_KEY3WxR) | Key 3 Word x Register |
0x40 | TDES_IDATAxR[2] (TDES_IDATAxR) | Input Data x Register |
0x50 | TDES_ODATAxR[2] (TDES_ODATAxR) | Output Data x Register |
0x60 | TDES_IVxR[2] (TDES_IVxR) | Initialization Vector x Register |
0xFC | TDES_VR | TDES Version Register |
0x100 | TDES_RPR (PDC_RPR) | Receive Pointer Register |
0x104 | TDES_RCR (PDC_RCR) | Receive Counter Register |
0x108 | TDES_TPR (PDC_TPR) | Transmit Pointer Register |
0x10C | TDES_TCR (PDC_TCR) | Transmit Counter Register |
0x110 | TDES_RNPR (PDC_RNPR) | Receive Next Pointer Register |
0x114 | TDES_RNCR (PDC_RNCR) | Receive Next Counter Register |
0x118 | TDES_TNPR (PDC_TNPR) | Transmit Next Pointer Register |
0x11C | TDES_TNCR (PDC_TNCR) | Transmit Next Counter Register |
0x120 | TDES_PTCR (PDC_PTCR) | PDC Transfer Control Register |
0x124 | TDES_PTSR (PDC_PTSR) | PDC Transfer Status Register |
Function | Description |
---|---|
AT91F_TDES_IsInterruptMasked | Test if TDES Interrupt is Masked |
AT91F_TDES_EnableIt | Enable TDES interrupt |
AT91F_TDES_SetInitializationVector | Set Initialization Vector x |
AT91F_TDES_SoftReset | Reset TDES |
AT91F_TDES_GetInterruptMaskStatus | Return TDES Interrupt Mask Status |
AT91F_TDES_GetModeReg | Return the Mode Register of the TDES controller value |
AT91F_TDES_GetOutputData | Get Output Data x |
AT91F_TDES_InputData | Set Input Data x |
AT91F_TDES_SetCryptoKey1 | Set Cryptographic Key 1 Word x |
AT91F_TDES_SetCryptoKey2 | Set Cryptographic Key 2 Word x |
AT91F_TDES_SetCryptoKey3 | Set Cryptographic Key 3 Word x |
AT91F_TDES_StartProcessing | Start Encryption or Decryption |
AT91F_TDES_IsStatusSet | Test if TDES Status is Set |
AT91F_TDES_CfgModeReg | Configure the Mode Register of the TDES controller |
AT91F_TDES_DisableIt | Disable TDES interrupt |
AT91F_TDES_GetStatus | Return TDES Interrupt Status |
Offset | Name | Description |
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0 | TDES_START AT91C_TDES_START | Starts Processing 0 = No effect. 1 = Start Encryption/Decryption process. |
8 | TDES_SWRST AT91C_TDES_SWRST | Software Reset 0 = No effect. 1 = Resets the TDES. A software triggered hardware reset of the TDES interface is performed. |
Offset | Name | Description | |||||||||||||||
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0 | TDES_CIPHER AT91C_TDES_CIPHER | Processing Mode 0 = Decrypts Data. 1 = Encrypts Data. | |||||||||||||||
1 | TDES_TDESMOD AT91C_TDES_TDESMOD | Single or Triple DES Mode 0: Single DES processing using TDES_KEY1WxR registers. 1: Triple DES processing using TDES_KEY1WxR, TDES_KEY2WxR and TDES_KEY3WxR registers. | |||||||||||||||
4 | TDES_KEYMOD AT91C_TDES_KEYMOD | Key Mode 0: Three-key algorithm is selected. 1: Two-key algorithm is selected. There is no need to write TDES_KEY3WxR registers. | |||||||||||||||
9..8 | TDES_SMOD AT91C_TDES_SMOD | Start Mode
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13..12 | TDES_OPMOD AT91C_TDES_OPMOD | Operation Mode
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15 | TDES_LOD AT91C_TDES_LOD | Last Output Data Mode 0 = No effect. In Manual and Auto modes, the DATRDY flag is cleared when at least one of the Output Data registers is read. 1 = The DATRDY flag is cleared when at least one of the Input Data Registers is written. No more Output Data Register reads is necessary between consecutive encryptions/decryptions. | |||||||||||||||
17..16 | TDES_CFBS AT91C_TDES_CFBS | Cipher Feedback Data Size
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Offset | Name | Description |
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0 | TDES_DATRDY AT91C_TDES_DATRDY | DATRDY 0 = No effect. 1 = En/Dis/Mask/Status of DATRDY (for Manual and Auto Mode in TDES_MR). |
1 | TDES_ENDRX AT91C_TDES_ENDRX | PDC Read Buffer End 0 = The Receive Counter Register has not reached 0 since the last write in TDES_RCR or TDES_RNCR. 1 = The Receive Counter Register has reached 0 since the last write in TDES_RCR or TDES_RNCR. |
2 | TDES_ENDTX AT91C_TDES_ENDTX | PDC Write Buffer End 0 = The Transmit Counter Register has not reached 0 since the last write in TDES_TCR or TDES_TNCR. 1 = The Transmit Counter Register has reached 0 since the last write in TDES_TCR or TDES_TNCR. |
3 | TDES_RXBUFF AT91C_TDES_RXBUFF | PDC Read Buffer Full 0 = TDES_RCR or TDES_RNCR has a value other than 0. 1 = Both TDES_RCR and TDES_RNCR has a value of 0. |
4 | TDES_TXBUFE AT91C_TDES_TXBUFE | PDC Write Buffer Empty 0 = TDES_TCR or TDES_TNCR has a value other than 0. 1 = Both TDES_TCR and TDES_TNCR has a value of 0. |
8 | TDES_URAD AT91C_TDES_URAD | Unspecified Register Access Detection 0 = No unspecified register access has been detected since the last SWRST. 1 = At least one unspecified register access has been detected since the last SWRST. |
Offset | Name | Description |
---|---|---|
0 | TDES_DATRDY AT91C_TDES_DATRDY | DATRDY 0 = No effect. 1 = En/Dis/Mask/Status of DATRDY (for Manual and Auto Mode in TDES_MR). |
1 | TDES_ENDRX AT91C_TDES_ENDRX | PDC Read Buffer End 0 = The Receive Counter Register has not reached 0 since the last write in TDES_RCR or TDES_RNCR. 1 = The Receive Counter Register has reached 0 since the last write in TDES_RCR or TDES_RNCR. |
2 | TDES_ENDTX AT91C_TDES_ENDTX | PDC Write Buffer End 0 = The Transmit Counter Register has not reached 0 since the last write in TDES_TCR or TDES_TNCR. 1 = The Transmit Counter Register has reached 0 since the last write in TDES_TCR or TDES_TNCR. |
3 | TDES_RXBUFF AT91C_TDES_RXBUFF | PDC Read Buffer Full 0 = TDES_RCR or TDES_RNCR has a value other than 0. 1 = Both TDES_RCR and TDES_RNCR has a value of 0. |
4 | TDES_TXBUFE AT91C_TDES_TXBUFE | PDC Write Buffer Empty 0 = TDES_TCR or TDES_TNCR has a value other than 0. 1 = Both TDES_TCR and TDES_TNCR has a value of 0. |
8 | TDES_URAD AT91C_TDES_URAD | Unspecified Register Access Detection 0 = No unspecified register access has been detected since the last SWRST. 1 = At least one unspecified register access has been detected since the last SWRST. |
Offset | Name | Description |
---|---|---|
0 | TDES_DATRDY AT91C_TDES_DATRDY | DATRDY 0 = No effect. 1 = En/Dis/Mask/Status of DATRDY (for Manual and Auto Mode in TDES_MR). |
1 | TDES_ENDRX AT91C_TDES_ENDRX | PDC Read Buffer End 0 = The Receive Counter Register has not reached 0 since the last write in TDES_RCR or TDES_RNCR. 1 = The Receive Counter Register has reached 0 since the last write in TDES_RCR or TDES_RNCR. |
2 | TDES_ENDTX AT91C_TDES_ENDTX | PDC Write Buffer End 0 = The Transmit Counter Register has not reached 0 since the last write in TDES_TCR or TDES_TNCR. 1 = The Transmit Counter Register has reached 0 since the last write in TDES_TCR or TDES_TNCR. |
3 | TDES_RXBUFF AT91C_TDES_RXBUFF | PDC Read Buffer Full 0 = TDES_RCR or TDES_RNCR has a value other than 0. 1 = Both TDES_RCR and TDES_RNCR has a value of 0. |
4 | TDES_TXBUFE AT91C_TDES_TXBUFE | PDC Write Buffer Empty 0 = TDES_TCR or TDES_TNCR has a value other than 0. 1 = Both TDES_TCR and TDES_TNCR has a value of 0. |
8 | TDES_URAD AT91C_TDES_URAD | Unspecified Register Access Detection 0 = No unspecified register access has been detected since the last SWRST. 1 = At least one unspecified register access has been detected since the last SWRST. |
Offset | Name | Description | |||||||||||||||
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0 | TDES_DATRDY AT91C_TDES_DATRDY | DATRDY 0 = No effect. 1 = En/Dis/Mask/Status of DATRDY (for Manual and Auto Mode in TDES_MR). | |||||||||||||||
1 | TDES_ENDRX AT91C_TDES_ENDRX | PDC Read Buffer End 0 = The Receive Counter Register has not reached 0 since the last write in TDES_RCR or TDES_RNCR. 1 = The Receive Counter Register has reached 0 since the last write in TDES_RCR or TDES_RNCR. | |||||||||||||||
2 | TDES_ENDTX AT91C_TDES_ENDTX | PDC Write Buffer End 0 = The Transmit Counter Register has not reached 0 since the last write in TDES_TCR or TDES_TNCR. 1 = The Transmit Counter Register has reached 0 since the last write in TDES_TCR or TDES_TNCR. | |||||||||||||||
3 | TDES_RXBUFF AT91C_TDES_RXBUFF | PDC Read Buffer Full 0 = TDES_RCR or TDES_RNCR has a value other than 0. 1 = Both TDES_RCR and TDES_RNCR has a value of 0. | |||||||||||||||
4 | TDES_TXBUFE AT91C_TDES_TXBUFE | PDC Write Buffer Empty 0 = TDES_TCR or TDES_TNCR has a value other than 0. 1 = Both TDES_TCR and TDES_TNCR has a value of 0. | |||||||||||||||
8 | TDES_URAD AT91C_TDES_URAD | Unspecified Register Access Detection 0 = No unspecified register access has been detected since the last SWRST. 1 = At least one unspecified register access has been detected since the last SWRST. | |||||||||||||||
13..12 | TDES_URAT AT91C_TDES_URAT | Unspecified Register Access Type Status Only the last Unspecified Register Access Type is available through the URAT field.
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