Ethernet MAC 10/100 Peripheral

EMAC (AT91S_EMAC) 0xFFFDC000 (AT91C_BASE_EMAC)
Periph ID AICSymbolDescription
16 (AT91C_ID_EMAC)Ethernet MAC

SignalSymbolPIO controllerDescription
ETX0(AT91C_PB2_ETX0 )PIOB Periph: A Bit: 2Ethernet MAC Transmit Data 0
ETXER(AT91C_PB12_ETXER )PIOB Periph: A Bit: 12Ethernet MAC Transmikt Coding Error
ECOL(AT91C_PB16_ECOL )PIOB Periph: A Bit: 16Ethernet MAC Collision Detected
ERXDV_ECRSDV(AT91C_PB15_ERXDV_ECRSDV)PIOB Periph: A Bit: 15Ethernet MAC Receive Data Valid
ETX3(AT91C_PB11_ETX3 )PIOB Periph: A Bit: 11Ethernet MAC Transmit Data 3
ERX1(AT91C_PB6_ERX1 )PIOB Periph: A Bit: 6Ethernet MAC Receive Data 1
ERX2(AT91C_PB13_ERX2 )PIOB Periph: A Bit: 13Ethernet MAC Receive Data 2
ETX1(AT91C_PB3_ETX1 )PIOB Periph: A Bit: 3Ethernet MAC Transmit Data 1
ECRS(AT91C_PB4_ECRS )PIOB Periph: A Bit: 4Ethernet MAC Carrier Sense/Carrier Sense and Data Valid
EMDC(AT91C_PB8_EMDC )PIOB Periph: A Bit: 8Ethernet MAC Management Data Clock
ERX0(AT91C_PB5_ERX0 )PIOB Periph: A Bit: 5Ethernet MAC Receive Data 0
EF100(AT91C_PB18_EF100 )PIOB Periph: A Bit: 18Ethernet MAC Force 100 Mbits/sec
ERX3(AT91C_PB14_ERX3 )PIOB Periph: A Bit: 14Ethernet MAC Receive Data 3
ETXEN(AT91C_PB1_ETXEN )PIOB Periph: A Bit: 1Ethernet MAC Transmit Enable
ETX2(AT91C_PB10_ETX2 )PIOB Periph: A Bit: 10Ethernet MAC Transmit Data 2
ETXCK_EREFCK(AT91C_PB0_ETXCK_EREFCK)PIOB Periph: A Bit: 0Ethernet MAC Transmit Clock/Reference Clock
EMDIO(AT91C_PB9_EMDIO )PIOB Periph: A Bit: 9Ethernet MAC Management Data Input/Output
ERXER(AT91C_PB7_ERXER )PIOB Periph: A Bit: 7Ethernet MAC Receive Error
ERXCK(AT91C_PB17_ERXCK )PIOB Periph: A Bit: 17Ethernet MAC Receive Clock

FunctionDescription
AT91F_EMAC_CfgPIOConfigure PIO controllers to drive EMAC signals
AT91F_EMAC_CfgPMCEnable Peripheral clock in PMC for EMAC


EMAC Software API (AT91S_EMAC)

OffsetFieldDescription
0x0EMAC_NCRNetwork Control Register
0x4EMAC_NCFGRNetwork Configuration Register
0x8EMAC_NSRNetwork Status Register
0x14EMAC_TSRTransmit Status Register
0x18EMAC_RBQPReceive Buffer Queue Pointer
0x1CEMAC_TBQPTransmit Buffer Queue Pointer
0x20EMAC_RSRReceive Status Register
0x24EMAC_ISRInterrupt Status Register
0x28EMAC_IERInterrupt Enable Register
0x2CEMAC_IDRInterrupt Disable Register
0x30EMAC_IMRInterrupt Mask Register
0x34EMAC_MANPHY Maintenance Register
0x38EMAC_PTRPause Time Register
0x3CEMAC_PFRPause Frames received Register
0x40EMAC_FTOFrames Transmitted OK Register
0x44EMAC_SCFSingle Collision Frame Register
0x48EMAC_MCFMultiple Collision Frame Register
0x4CEMAC_FROFrames Received OK Register
0x50EMAC_FCSEFrame Check Sequence Error Register
0x54EMAC_ALEAlignment Error Register
0x58EMAC_DTFDeferred Transmission Frame Register
0x5CEMAC_LCOLLate Collision Register
0x60EMAC_ECOLExcessive Collision Register
0x64EMAC_TUNDTransmit Underrun Error Register
0x68EMAC_CSECarrier Sense Error Register
0x6CEMAC_RREReceive Ressource Error Register
0x70EMAC_ROVReceive Overrun Errors Register
0x74EMAC_RSEReceive Symbol Errors Register
0x78EMAC_ELEExcessive Length Errors Register
0x7CEMAC_RJAReceive Jabbers Register
0x80EMAC_USFUndersize Frames Register
0x84EMAC_STESQE Test Error Register
0x88EMAC_RLEReceive Length Field Mismatch Register
0x8CEMAC_TPFTransmitted Pause Frames Register
0x90EMAC_HRBHash Address Bottom[31:0]
0x94EMAC_HRTHash Address Top[63:32]
0x98EMAC_SA1L (EMAC_SA1B)Specific Address 1 Bottom, First 4 bytes
0x9CEMAC_SA1H (EMAC_SA1T)Specific Address 1 Top, Last 2 bytes
0xA0EMAC_SA2L (EMAC_SA2B)Specific Address 2 Bottom, First 4 bytes
0xA4EMAC_SA2H (EMAC_SA2T)Specific Address 2 Top, Last 2 bytes
0xA8EMAC_SA3L (EMAC_SA3B)Specific Address 3 Bottom, First 4 bytes
0xACEMAC_SA3H (EMAC_SA3T)Specific Address 3 Top, Last 2 bytes
0xB0EMAC_SA4L (EMAC_SA4B)Specific Address 4 Bottom, First 4 bytes
0xB4EMAC_SA4H (EMAC_SA4T)Specific Address 4 Top, Last 2 bytes
0xB8EMAC_TIDType ID Checking Register
0xBCEMAC_TPQTransmit Pause Quantum Register
0xC0EMAC_USRIOUSER Input/Output Register
0xC4EMAC_WOLWake On LAN Register
0xFCEMAC_REVRevision Register

EMAC Register Description

EMAC: AT91_REG EMAC_NCR Network Control Register


Network Control Register
OffsetNameDescription
0EMAC_LB
AT91C_EMAC_LB
Loopback. Optional. When set, loopback signal is at high level.
1EMAC_LLB
AT91C_EMAC_LLB
Loopback local.
When set, connects ETX[3:0] to ERX[3:0], ETXEN to ERXDV, forces full duplex and drives ERXCK and ETXCK_REFCK with HCLK divided by 4.
2EMAC_RE
AT91C_EMAC_RE
Receive enable.
When set, enables the Ethernet MAC to receive data.
3EMAC_TE
AT91C_EMAC_TE
Transmit enable.
When set, enables the Ethernet transmitter to send data.
4EMAC_MPE
AT91C_EMAC_MPE
Management port enable.
Set to one to enable the management port. When zero, forces MDIO to high impedance state.
5EMAC_CLRSTAT
AT91C_EMAC_CLRSTAT
Clear statistics registers.
This bit is write-only. Writing a one clears the statistics registers.
6EMAC_INCSTAT
AT91C_EMAC_INCSTAT
Increment statistics registers.
This bit is write-only. Writing a one increments all the statistics registers by one for test purposes.
7EMAC_WESTAT
AT91C_EMAC_WESTAT
Write enable for statistics registers.
Setting this bit to one makes the statistics registers writable for functional test purposes.
8EMAC_BP
AT91C_EMAC_BP
Back pressure.
If this field is set, then in half-duplex mode collisions are forced on all received frames by transmitting 64 bits of data (default pattern).
9EMAC_TSTART
AT91C_EMAC_TSTART
Start Transmission.
Writing one to this bit starts transmission.
10EMAC_THALT
AT91C_EMAC_THALT
Transmission Halt.
Writing one to this bit halts transmission as soon as any ongoing frame transmission ends.
11EMAC_TPFR
AT91C_EMAC_TPFR
Transmit pause frame
Writing one to this bit transmits a pause frame with the pause quantum from the transmit pause quantum register at the next available transmitter idle time.
12EMAC_TZQ
AT91C_EMAC_TZQ
Transmit zero quantum pause frame
Writing a one to this bit transmits a pause frame with zero pause quantum at the next available transmitter idle time.

EMAC: AT91_REG EMAC_NCFGR Network Configuration Register

OffsetNameDescription
0EMAC_SPD
AT91C_EMAC_SPD
Speed.
Set to 1 to indicate 100 Mbit/sec. operation, 0 for 10 Mbit/sec. Has no other functional effect.
1EMAC_FD
AT91C_EMAC_FD
Full duplex.
If set to 1, the transmit block ignores the state of collision and carrier sense and allows receive while transmitting.
3EMAC_JFRAME
AT91C_EMAC_JFRAME
Jumbo Frames.
Not implemented. Set to one to enable jumbo frames of up to 10240 bytes to be accepted.
4EMAC_CAF
AT91C_EMAC_CAF
Copy all frames.
When set to 1, all valid frames are received.
5EMAC_NBC
AT91C_EMAC_NBC
No broadcast.
When set to 1, frames addressed to the broadcast address of all ones are not received.
6EMAC_MTI
AT91C_EMAC_MTI
Multicast hash event enable
When set, multicast hash events causes the wol output to be asserted.
7EMAC_UNI
AT91C_EMAC_UNI
Unicast hash enable.
When set, unicast frames are received when six bits of the CRC of the destination address point to a bit that is set in the hash register.
8EMAC_BIG
AT91C_EMAC_BIG
Receive 1522 bytes.
When set, the MAC receives up to 1522 bytes. Normally the MAC receives frames up to 1518 bytes in length.
9EMAC_EAE
AT91C_EMAC_EAE
External address match enable.
Optional.
11..10EMAC_CLK
AT91C_EMAC_CLK

The system clock (HCLK) is divided down to generate MDC (the clock for the MDIO). To conform with IEEE standard 802.3 MDC must not exceed 2.5 MHz. At reset this field is set to 10 so that HCLK is divided by 32.
ValueLabelDescription
0EMAC_CLK_HCLK_8
AT91C_EMAC_CLK_HCLK_8

HCLK divided by 8
1EMAC_CLK_HCLK_16
AT91C_EMAC_CLK_HCLK_16

HCLK divided by 16
2EMAC_CLK_HCLK_32
AT91C_EMAC_CLK_HCLK_32

HCLK divided by 32
3EMAC_CLK_HCLK_64
AT91C_EMAC_CLK_HCLK_64

HCLK divided by 64
12EMAC_RTY
AT91C_EMAC_RTY

Retry test. When set, the time between frames is always one time slot. For test purposes only. Must be cleared for normal operation.
13EMAC_PAE
AT91C_EMAC_PAE

Pause Enable. When set, transmission pauses when a valid pause frame is received.
15..14EMAC_RBOF
AT91C_EMAC_RBOF

The system clock (HCLK) is divided down to generate MDC (the clock for the MDIO). To conform with IEEE standard 802.3 MDC must not exceed 2.5 MHz. At reset this field is set to 10 so that HCLK is divided by 32.
ValueLabelDescription
0EMAC_RBOF_OFFSET_0
AT91C_EMAC_RBOF_OFFSET_0

no offset from start of receive buffer
1EMAC_RBOF_OFFSET_1
AT91C_EMAC_RBOF_OFFSET_1

one byte offset from start of receive buffer
2EMAC_RBOF_OFFSET_2
AT91C_EMAC_RBOF_OFFSET_2

two bytes offset from start of receive buffer
3EMAC_RBOF_OFFSET_3
AT91C_EMAC_RBOF_OFFSET_3

three bytes offset from start of receive buffer
16EMAC_RLCE
AT91C_EMAC_RLCE
Receive Length field Checking Enable
When set, frames with measured lengths shorter than their length fields are discarded.
17EMAC_DRFCS
AT91C_EMAC_DRFCS
Discard Receive FCS
When set, the FCS field of received frames are not be copied to memory.
18EMAC_EFRHD
AT91C_EMAC_EFRHD

Enable frames to be received in half-duplex mode while transmitting.
19EMAC_IRXFCS
AT91C_EMAC_IRXFCS
Ignore RX FCS
When set, frames with FCS/CRC errors are not rejected and no FCS error statistics are counted. For normal operation, this bit must be set to 0.

EMAC: AT91_REG EMAC_NSR Network Status Register

OffsetNameDescription
0EMAC_LINKR
AT91C_EMAC_LINKR

Reserved
1EMAC_MDIO
AT91C_EMAC_MDIO

0 = MDIO pin is not set
1 = MDIO pin set
2EMAC_IDLE
AT91C_EMAC_IDLE

0 = PHY logic is idle
1 = PHY logic is running

EMAC: AT91_REG EMAC_TSR Transmit Status Register

OffsetNameDescription
0EMAC_UBR
AT91C_EMAC_UBR

Used Bit Read. Set when a transmit buffer descriptor is read with its used bit set. Cleared by writing a one to this bit.
1EMAC_COL
AT91C_EMAC_COL

Collision occurred. Set by the assertion of collision. Cleared by writing a one to this bit.
2EMAC_RLES
AT91C_EMAC_RLES

Retry limit exceeded. Cleared by writing a one to this bit.
3EMAC_TGO
AT91C_EMAC_TGO
Transmit Go
Transmit Go. If high transmit is active.
4EMAC_BEX
AT91C_EMAC_BEX
Buffers exhausted mid frame
Buffers exhausted mid frame. if the buffers run out during transmission of a frame then transmission stops, FCS shall be bad and tx_er asserted. Cleared by writing a one to this bit.
5EMAC_COMP
AT91C_EMAC_COMP

Transmit complete. Set when a frame has been transmitted. Cleared by writing a one to this bit.
6EMAC_UND
AT91C_EMAC_UND

Transmit underrun. Set when transmit DMA was not able to read data from memory in time. If this happens, the transmitter forces bad CRC. Cleared by writing a one to this bit.

EMAC: AT91_REG EMAC_RBQP Receive Buffer Queue Pointer


Receive buffer queue pointer. Written with the address of the start of the receive queue, reads as a pointer to the current buffer being used. The receive buffer is forced to word alignment.

EMAC: AT91_REG EMAC_TBQP Transmit Buffer Queue Pointer


Transmit buffer queue pointer.Written with the address of the start of the transmit queue, reads as a pointer to the first buffer of the frame being transmitted or about to be transmitted.

EMAC: AT91_REG EMAC_RSR Receive Status Register

OffsetNameDescription
0EMAC_BNA
AT91C_EMAC_BNA

Buffer not available. An attempt was made to get a new buffer and the pointer indicated that it was owned by the processor. The DMA rereads the pointer each time a new frame starts until a valid pointer is found. This bit is set at each attempt that fails even if it has not had a successful pointer read since it has been cleared. Cleared by writing a one to this bit.
1EMAC_REC
AT91C_EMAC_REC

Frame received. One or more frames have been received and placed in memory. Cleared by writing a one to this bit.
2EMAC_OVR
AT91C_EMAC_OVR

RX overrun. The DMA block was unable to store the receive frame to memory, either because the ASB bus was not granted in time or because a not OK HRESP was returned. The buffer is recovered if this happens. Cleared by writing a one to this bit.

EMAC: AT91_REG EMAC_ISR Interrupt Status Register

OffsetNameDescription
0EMAC_MFD
AT91C_EMAC_MFD

Management Frame done. The PHY maintenance register has completed its operation. Cleared on read.
1EMAC_RCOMP
AT91C_EMAC_RCOMP

Receive complete. A frame has been stored in memory. Cleared on read.
2EMAC_RXUBR
AT91C_EMAC_RXUBR

Receive Used Bit read. Set when a receive buffer descriptor is read with its used bit set. Cleared on read.
3EMAC_TXUBR
AT91C_EMAC_TXUBR

Transmit Used Bit Read. Set when a transmit buffer descriptor is read with its used bit set. Cleared on read.
4EMAC_TUNDR
AT91C_EMAC_TUNDR

Transmit error. Ethernet transmit buffer underrun. The transmit DMA did not complete fetch frame data in time for it to be transmitted. Cleared on read.
5EMAC_RLEX
AT91C_EMAC_RLEX

Retry limit exceeded. Cleared on read.
6EMAC_TXERR
AT91C_EMAC_TXERR

Transmit buffers exhausted in mid-frame - transmit error. Cleared on read.
7EMAC_TCOMP
AT91C_EMAC_TCOMP

Transmit complete. Set when a frame has been transmitted. Cleared on read.
9EMAC_LINK
AT91C_EMAC_LINK

Set when LINK pin changes value. Optional.
10EMAC_ROVR
AT91C_EMAC_ROVR

RX overrun. Set when the RX overrun status bit is set. Cleared on read.
11EMAC_HRESP
AT91C_EMAC_HRESP

HRESP not OK. Set when the DMA block sees HRESP not OK. Cleared on read.
12EMAC_PFRE
AT91C_EMAC_PFRE

Indicates a valid pause has been received. Cleared on a read.
13EMAC_PTZ
AT91C_EMAC_PTZ

set when the pause time register, 0x38 decrements to zero. Cleared on a read.

EMAC: AT91_REG EMAC_IER Interrupt Enable Register

OffsetNameDescription
0EMAC_MFD
AT91C_EMAC_MFD

Management Frame done. The PHY maintenance register has completed its operation. Cleared on read.
1EMAC_RCOMP
AT91C_EMAC_RCOMP

Receive complete. A frame has been stored in memory. Cleared on read.
2EMAC_RXUBR
AT91C_EMAC_RXUBR

Receive Used Bit read. Set when a receive buffer descriptor is read with its used bit set. Cleared on read.
3EMAC_TXUBR
AT91C_EMAC_TXUBR

Transmit Used Bit Read. Set when a transmit buffer descriptor is read with its used bit set. Cleared on read.
4EMAC_TUNDR
AT91C_EMAC_TUNDR

Transmit error. Ethernet transmit buffer underrun. The transmit DMA did not complete fetch frame data in time for it to be transmitted. Cleared on read.
5EMAC_RLEX
AT91C_EMAC_RLEX

Retry limit exceeded. Cleared on read.
6EMAC_TXERR
AT91C_EMAC_TXERR

Transmit buffers exhausted in mid-frame - transmit error. Cleared on read.
7EMAC_TCOMP
AT91C_EMAC_TCOMP

Transmit complete. Set when a frame has been transmitted. Cleared on read.
9EMAC_LINK
AT91C_EMAC_LINK

Set when LINK pin changes value. Optional.
10EMAC_ROVR
AT91C_EMAC_ROVR

RX overrun. Set when the RX overrun status bit is set. Cleared on read.
11EMAC_HRESP
AT91C_EMAC_HRESP

HRESP not OK. Set when the DMA block sees HRESP not OK. Cleared on read.
12EMAC_PFRE
AT91C_EMAC_PFRE

Indicates a valid pause has been received. Cleared on a read.
13EMAC_PTZ
AT91C_EMAC_PTZ

set when the pause time register, 0x38 decrements to zero. Cleared on a read.

EMAC: AT91_REG EMAC_IDR Interrupt Disable Register

OffsetNameDescription
0EMAC_MFD
AT91C_EMAC_MFD

Management Frame done. The PHY maintenance register has completed its operation. Cleared on read.
1EMAC_RCOMP
AT91C_EMAC_RCOMP

Receive complete. A frame has been stored in memory. Cleared on read.
2EMAC_RXUBR
AT91C_EMAC_RXUBR

Receive Used Bit read. Set when a receive buffer descriptor is read with its used bit set. Cleared on read.
3EMAC_TXUBR
AT91C_EMAC_TXUBR

Transmit Used Bit Read. Set when a transmit buffer descriptor is read with its used bit set. Cleared on read.
4EMAC_TUNDR
AT91C_EMAC_TUNDR

Transmit error. Ethernet transmit buffer underrun. The transmit DMA did not complete fetch frame data in time for it to be transmitted. Cleared on read.
5EMAC_RLEX
AT91C_EMAC_RLEX

Retry limit exceeded. Cleared on read.
6EMAC_TXERR
AT91C_EMAC_TXERR

Transmit buffers exhausted in mid-frame - transmit error. Cleared on read.
7EMAC_TCOMP
AT91C_EMAC_TCOMP

Transmit complete. Set when a frame has been transmitted. Cleared on read.
9EMAC_LINK
AT91C_EMAC_LINK

Set when LINK pin changes value. Optional.
10EMAC_ROVR
AT91C_EMAC_ROVR

RX overrun. Set when the RX overrun status bit is set. Cleared on read.
11EMAC_HRESP
AT91C_EMAC_HRESP

HRESP not OK. Set when the DMA block sees HRESP not OK. Cleared on read.
12EMAC_PFRE
AT91C_EMAC_PFRE

Indicates a valid pause has been received. Cleared on a read.
13EMAC_PTZ
AT91C_EMAC_PTZ

set when the pause time register, 0x38 decrements to zero. Cleared on a read.

EMAC: AT91_REG EMAC_IMR Interrupt Mask Register


Important Note: The interrupt is masked (disabled) when the corresponding bit is set. This is non-standard for AT91 products as generally a mask bit set enables the interrupt.
OffsetNameDescription
0EMAC_MFD
AT91C_EMAC_MFD

Management Frame done. The PHY maintenance register has completed its operation. Cleared on read.
1EMAC_RCOMP
AT91C_EMAC_RCOMP

Receive complete. A frame has been stored in memory. Cleared on read.
2EMAC_RXUBR
AT91C_EMAC_RXUBR

Receive Used Bit read. Set when a receive buffer descriptor is read with its used bit set. Cleared on read.
3EMAC_TXUBR
AT91C_EMAC_TXUBR

Transmit Used Bit Read. Set when a transmit buffer descriptor is read with its used bit set. Cleared on read.
4EMAC_TUNDR
AT91C_EMAC_TUNDR

Transmit error. Ethernet transmit buffer underrun. The transmit DMA did not complete fetch frame data in time for it to be transmitted. Cleared on read.
5EMAC_RLEX
AT91C_EMAC_RLEX

Retry limit exceeded. Cleared on read.
6EMAC_TXERR
AT91C_EMAC_TXERR

Transmit buffers exhausted in mid-frame - transmit error. Cleared on read.
7EMAC_TCOMP
AT91C_EMAC_TCOMP

Transmit complete. Set when a frame has been transmitted. Cleared on read.
9EMAC_LINK
AT91C_EMAC_LINK

Set when LINK pin changes value. Optional.
10EMAC_ROVR
AT91C_EMAC_ROVR

RX overrun. Set when the RX overrun status bit is set. Cleared on read.
11EMAC_HRESP
AT91C_EMAC_HRESP

HRESP not OK. Set when the DMA block sees HRESP not OK. Cleared on read.
12EMAC_PFRE
AT91C_EMAC_PFRE

Indicates a valid pause has been received. Cleared on a read.
13EMAC_PTZ
AT91C_EMAC_PTZ

set when the pause time register, 0x38 decrements to zero. Cleared on a read.

EMAC: AT91_REG EMAC_MAN PHY Maintenance Register


Writing to this register starts the shift register that controls the serial connection to the PHY. On each shift cycle the MDIO pin becomes equal to the MSB of the shift register and LSB of the shift register becomes equal to the value of the MDIO pin. When the shifting is complete an interrupt is generated and the IDLE field is set in the Network Status register.
When read, gives current shifted value.
OffsetNameDescription
15..0EMAC_DATA
AT91C_EMAC_DATA

For a write operation this is written with the data to be written to the PHY. After a read operation this contains the data read from the PHY.
17..16EMAC_CODE
AT91C_EMAC_CODE

Must be written to 10 in accordance with IEEE standard 802.3. Reads as written.
22..18EMAC_REGA
AT91C_EMAC_REGA

Register address. Specifies the register in the PHY to access.
27..23EMAC_PHYA
AT91C_EMAC_PHYA

PHY address. Normally is 0.
29..28EMAC_RW
AT91C_EMAC_RW

Read/write Operation. 10 is read. 01 is write. Any other value is an invalid PHY management frame.
31..30EMAC_SOF
AT91C_EMAC_SOF

Must be written with 01 to make a valid PHY management frame. Conforms with IEEE standard 802.3.

EMAC: AT91_REG EMAC_PTR Pause Time Register


16-Bit Register which stores the current value of the pause time register which is decremented every 512 bit time.

EMAC: AT91_REG EMAC_PFR Pause Frames received Register


A 16-bit register counting the number of good pause frames received.

EMAC: AT91_REG EMAC_FTO Frames Transmitted OK Register


A 24-bit register counting the number of frames successfully transmitted.

EMAC: AT91_REG EMAC_SCF Single Collision Frame Register


A 16-bit register counting the number of frames experiencing a single collision before being transmitted and experiencing no carrier loss nor underrun.

EMAC: AT91_REG EMAC_MCF Multiple Collision Frame Register


A 16-bit register counting the number of frames experiencing between two and fifteen collisions prior to being transmitted (62 - 1518 bytes, no carrier loss, no underrun).

EMAC: AT91_REG EMAC_FRO Frames Received OK Register


A 24-bit register counting the number of good frames received, i.e., address recognized. A good frame is of length 64 to 1518 bytes and has no FCS, alignment or code errors.

EMAC: AT91_REG EMAC_FCSE Frame Check Sequence Error Register


An 8-bit register counting frames that are an integral number of bytes, have bad CRC and are between 64 and 1518 bytes in length (1536 if bit 8 set in network configuration register).

EMAC: AT91_REG EMAC_ALE Alignment Error Register


ETH_ALE An 8-bit register counting frames that:
- are address-recognized,
- are not an integral number of bytes long,
- have bad CRC when their length is truncated to an integral number of bytes,
- are between 64 and 1518 bytes long.

EMAC: AT91_REG EMAC_DTF Deferred Transmission Frame Register


A 16-bit register counting the number of frames experiencing deferral due to carrier sense active on their first attempt at transmission (no underrun or collision).

EMAC: AT91_REG EMAC_LCOL Late Collision Register


An 8-bit register counting the number of frames that experience a collision after the slot time (512 bits) has expired. No carrier loss or underrun. A late collision is counted twice, i.e., both as a collision and a late collision.

EMAC: AT91_REG EMAC_ECOL Excessive Collision Register


An 8-bit register counting the number of frames that failed to be transmitted because they experienced 16 collisions (64 - 1518 bytes, no carrier loss or underrun).

EMAC: AT91_REG EMAC_TUND Transmit Underrun Error Register


An 8-bit register counting the number of frames not transmitted due to a transmit DMA underrun. If this register is incremented, then no other register is incremented.

EMAC: AT91_REG EMAC_CSE Carrier Sense Error Register


An 8-bit register counting the number of frames for which carrier sense was not detected and that were maintained in half-duplex mode one slot time (512 bits) after the start of transmission (no excessive collision).

EMAC: AT91_REG EMAC_RRE Receive Ressource Error Register


A 16-bit register counting the number of frames that were address matched but could not be copied to memory because no receive buffer was available.

EMAC: AT91_REG EMAC_ROV Receive Overrun Errors Register


An 8-bit register counting the number of frames that are address recognized but were not copied to memory due to a receive DMA overrun.

EMAC: AT91_REG EMAC_RSE Receive Symbol Errors Register


An 8-bit register counting the number of frames that had rx_er asserted during reception.

EMAC: AT91_REG EMAC_ELE Excessive Length Errors Register


An 8-bit register counting the number of frames received exceeding 1518 bytes (1536 if bit 8 set in network configuration register)

EMAC: AT91_REG EMAC_RJA Receive Jabbers Register


An 8-bit register counting the number of frames received exceeding 1518 bytes in length and having either a CRC error, an alignment error or a code error.

EMAC: AT91_REG EMAC_USF Undersize Frames Register


An 8-bit register counting the number of frames received less that are than 64 bytes in length but that do not have either a CRC error, an alignment error or a code error.

EMAC: AT91_REG EMAC_STE SQE Test Error Register


An 8-bit register counting the number of frames where pin ECOL was not asserted within a slot time of pin ETXEN being deasserted.

EMAC: AT91_REG EMAC_RLE Receive Length Field Mismatch Register


An 8-bit register counting the number of frames received that have a measured length shorter than that extracted from its length field.

EMAC: AT91_REG EMAC_TPF Transmitted Pause Frames Register


A 16-bit register counting the number of pause frames transmitted.

EMAC: AT91_REG EMAC_HRB Hash Address Bottom[31:0]


Hash address bits 31 to 0

EMAC: AT91_REG EMAC_HRT Hash Address Top[63:32]


Hash address bits 63 to 32

EMAC: AT91_REG EMAC_SA1L Specific Address 1 Bottom, First 4 bytes


Specific address 1 bottom

EMAC: AT91_REG EMAC_SA1H Specific Address 1 Top, Last 2 bytes


Specific address 1 Top

EMAC: AT91_REG EMAC_SA2L Specific Address 2 Bottom, First 4 bytes


Specific address Bottom

EMAC: AT91_REG EMAC_SA2H Specific Address 2 Top, Last 2 bytes


Specific address Top

EMAC: AT91_REG EMAC_SA3L Specific Address 3 Bottom, First 4 bytes


Specific address Bottom

EMAC: AT91_REG EMAC_SA3H Specific Address 3 Top, Last 2 bytes


Specific address Top

EMAC: AT91_REG EMAC_SA4L Specific Address 4 Bottom, First 4 bytes


Specific address Bottom

EMAC: AT91_REG EMAC_SA4H Specific Address 4 Top, Last 2 bytes


Specific address Top

EMAC: AT91_REG EMAC_TID Type ID Checking Register


A 16-bit register to use in comparisons with received frames TypeID/Length field.

EMAC: AT91_REG EMAC_TPQ Transmit Pause Quantum Register


A 16-bit register.Used in hardware generation of transmitted pause frames as value for pause quantum.

EMAC: AT91_REG EMAC_USRIO USER Input/Output Register


This register exist if 'macb_user_io' verilog configuration option is set. When writing to the 16 lower bits, it drives user_out(15:0) bus.
When reading the 16 upper bits, it gives current user_in(15:0) value.
OffsetNameDescription
0EMAC_RMII
AT91C_EMAC_RMII
Reduce MII
When set, this bit enables the RMII operation mode. When reset, it selects the MII mode.
1EMAC_CLKEN
AT91C_EMAC_CLKEN
Clock Enable
When set, this bit enables the transceiver input clock. Setting this bit to 0 reduces power consumption.

EMAC: AT91_REG EMAC_WOL Wake On LAN Register

OffsetNameDescription
15..0EMAC_IP
AT91C_EMAC_IP
ARP request IP address
Written to define the least significant 16 bits of the target IP address that is matched to generate a Wake-on-LAN event.
16EMAC_MAG
AT91C_EMAC_MAG
Magic packet event enable
When set, magic packet events causes the wol output to be asserted.
17EMAC_ARP
AT91C_EMAC_ARP
ARP request event enable
When set, ARP request events causes the wol output to be asserted.
18EMAC_SA1
AT91C_EMAC_SA1
Specific address register 1 event enable
When set, specific address 1 events causes the wol output to be asserted.
19EMAC_MTI
AT91C_EMAC_MTI
Multicast hash event enable
When set, multicast hash events causes the wol output to be asserted.

EMAC: AT91_REG EMAC_REV Revision Register


Read-only register.
When read, 16 upper bits give MACB part reference (always 0x0001), and 16 lower bits give the revision number.
OffsetNameDescription
15..0EMAC_REVREF
AT91C_EMAC_REVREF

Read-only. After a read operation this contains the revision reference value.
31..16EMAC_PARTREF
AT91C_EMAC_PARTREF

Read-only. After a read operation this contains the part reference value, always 0x0001.