Periph ID AIC | Symbol | Description |
---|---|---|
16 | (AT91C_ID_EMAC) | Ethernet MAC |
Signal | Symbol | PIO controller | Description |
---|---|---|---|
ETX0 | (AT91C_PB2_ETX0 ) | PIOB Periph: A Bit: 2 | Ethernet MAC Transmit Data 0 |
ETXER | (AT91C_PB12_ETXER ) | PIOB Periph: A Bit: 12 | Ethernet MAC Transmikt Coding Error |
ECOL | (AT91C_PB16_ECOL ) | PIOB Periph: A Bit: 16 | Ethernet MAC Collision Detected |
ERXDV_ECRSDV | (AT91C_PB15_ERXDV_ECRSDV) | PIOB Periph: A Bit: 15 | Ethernet MAC Receive Data Valid |
ETX3 | (AT91C_PB11_ETX3 ) | PIOB Periph: A Bit: 11 | Ethernet MAC Transmit Data 3 |
ERX1 | (AT91C_PB6_ERX1 ) | PIOB Periph: A Bit: 6 | Ethernet MAC Receive Data 1 |
ERX2 | (AT91C_PB13_ERX2 ) | PIOB Periph: A Bit: 13 | Ethernet MAC Receive Data 2 |
ETX1 | (AT91C_PB3_ETX1 ) | PIOB Periph: A Bit: 3 | Ethernet MAC Transmit Data 1 |
ECRS | (AT91C_PB4_ECRS ) | PIOB Periph: A Bit: 4 | Ethernet MAC Carrier Sense/Carrier Sense and Data Valid |
EMDC | (AT91C_PB8_EMDC ) | PIOB Periph: A Bit: 8 | Ethernet MAC Management Data Clock |
ERX0 | (AT91C_PB5_ERX0 ) | PIOB Periph: A Bit: 5 | Ethernet MAC Receive Data 0 |
EF100 | (AT91C_PB18_EF100 ) | PIOB Periph: A Bit: 18 | Ethernet MAC Force 100 Mbits/sec |
ERX3 | (AT91C_PB14_ERX3 ) | PIOB Periph: A Bit: 14 | Ethernet MAC Receive Data 3 |
ETXEN | (AT91C_PB1_ETXEN ) | PIOB Periph: A Bit: 1 | Ethernet MAC Transmit Enable |
ETX2 | (AT91C_PB10_ETX2 ) | PIOB Periph: A Bit: 10 | Ethernet MAC Transmit Data 2 |
ETXCK_EREFCK | (AT91C_PB0_ETXCK_EREFCK) | PIOB Periph: A Bit: 0 | Ethernet MAC Transmit Clock/Reference Clock |
EMDIO | (AT91C_PB9_EMDIO ) | PIOB Periph: A Bit: 9 | Ethernet MAC Management Data Input/Output |
ERXER | (AT91C_PB7_ERXER ) | PIOB Periph: A Bit: 7 | Ethernet MAC Receive Error |
ERXCK | (AT91C_PB17_ERXCK ) | PIOB Periph: A Bit: 17 | Ethernet MAC Receive Clock |
Function | Description |
---|---|
AT91F_EMAC_CfgPIO | Configure PIO controllers to drive EMAC signals |
AT91F_EMAC_CfgPMC | Enable Peripheral clock in PMC for EMAC |
Offset | Field | Description |
---|---|---|
0x0 | EMAC_NCR | Network Control Register |
0x4 | EMAC_NCFGR | Network Configuration Register |
0x8 | EMAC_NSR | Network Status Register |
0x14 | EMAC_TSR | Transmit Status Register |
0x18 | EMAC_RBQP | Receive Buffer Queue Pointer |
0x1C | EMAC_TBQP | Transmit Buffer Queue Pointer |
0x20 | EMAC_RSR | Receive Status Register |
0x24 | EMAC_ISR | Interrupt Status Register |
0x28 | EMAC_IER | Interrupt Enable Register |
0x2C | EMAC_IDR | Interrupt Disable Register |
0x30 | EMAC_IMR | Interrupt Mask Register |
0x34 | EMAC_MAN | PHY Maintenance Register |
0x38 | EMAC_PTR | Pause Time Register |
0x3C | EMAC_PFR | Pause Frames received Register |
0x40 | EMAC_FTO | Frames Transmitted OK Register |
0x44 | EMAC_SCF | Single Collision Frame Register |
0x48 | EMAC_MCF | Multiple Collision Frame Register |
0x4C | EMAC_FRO | Frames Received OK Register |
0x50 | EMAC_FCSE | Frame Check Sequence Error Register |
0x54 | EMAC_ALE | Alignment Error Register |
0x58 | EMAC_DTF | Deferred Transmission Frame Register |
0x5C | EMAC_LCOL | Late Collision Register |
0x60 | EMAC_ECOL | Excessive Collision Register |
0x64 | EMAC_TUND | Transmit Underrun Error Register |
0x68 | EMAC_CSE | Carrier Sense Error Register |
0x6C | EMAC_RRE | Receive Ressource Error Register |
0x70 | EMAC_ROV | Receive Overrun Errors Register |
0x74 | EMAC_RSE | Receive Symbol Errors Register |
0x78 | EMAC_ELE | Excessive Length Errors Register |
0x7C | EMAC_RJA | Receive Jabbers Register |
0x80 | EMAC_USF | Undersize Frames Register |
0x84 | EMAC_STE | SQE Test Error Register |
0x88 | EMAC_RLE | Receive Length Field Mismatch Register |
0x8C | EMAC_TPF | Transmitted Pause Frames Register |
0x90 | EMAC_HRB | Hash Address Bottom[31:0] |
0x94 | EMAC_HRT | Hash Address Top[63:32] |
0x98 | EMAC_SA1L (EMAC_SA1B) | Specific Address 1 Bottom, First 4 bytes |
0x9C | EMAC_SA1H (EMAC_SA1T) | Specific Address 1 Top, Last 2 bytes |
0xA0 | EMAC_SA2L (EMAC_SA2B) | Specific Address 2 Bottom, First 4 bytes |
0xA4 | EMAC_SA2H (EMAC_SA2T) | Specific Address 2 Top, Last 2 bytes |
0xA8 | EMAC_SA3L (EMAC_SA3B) | Specific Address 3 Bottom, First 4 bytes |
0xAC | EMAC_SA3H (EMAC_SA3T) | Specific Address 3 Top, Last 2 bytes |
0xB0 | EMAC_SA4L (EMAC_SA4B) | Specific Address 4 Bottom, First 4 bytes |
0xB4 | EMAC_SA4H (EMAC_SA4T) | Specific Address 4 Top, Last 2 bytes |
0xB8 | EMAC_TID | Type ID Checking Register |
0xBC | EMAC_TPQ | Transmit Pause Quantum Register |
0xC0 | EMAC_USRIO | USER Input/Output Register |
0xC4 | EMAC_WOL | Wake On LAN Register |
0xFC | EMAC_REV | Revision Register |
Offset | Name | Description |
---|---|---|
0 | EMAC_LB AT91C_EMAC_LB | Loopback. Optional. When set, loopback signal is at high level. |
1 | EMAC_LLB AT91C_EMAC_LLB | Loopback local. When set, connects ETX[3:0] to ERX[3:0], ETXEN to ERXDV, forces full duplex and drives ERXCK and ETXCK_REFCK with HCLK divided by 4. |
2 | EMAC_RE AT91C_EMAC_RE | Receive enable. When set, enables the Ethernet MAC to receive data. |
3 | EMAC_TE AT91C_EMAC_TE | Transmit enable. When set, enables the Ethernet transmitter to send data. |
4 | EMAC_MPE AT91C_EMAC_MPE | Management port enable. Set to one to enable the management port. When zero, forces MDIO to high impedance state. |
5 | EMAC_CLRSTAT AT91C_EMAC_CLRSTAT | Clear statistics registers. This bit is write-only. Writing a one clears the statistics registers. |
6 | EMAC_INCSTAT AT91C_EMAC_INCSTAT | Increment statistics registers. This bit is write-only. Writing a one increments all the statistics registers by one for test purposes. |
7 | EMAC_WESTAT AT91C_EMAC_WESTAT | Write enable for statistics registers. Setting this bit to one makes the statistics registers writable for functional test purposes. |
8 | EMAC_BP AT91C_EMAC_BP | Back pressure. If this field is set, then in half-duplex mode collisions are forced on all received frames by transmitting 64 bits of data (default pattern). |
9 | EMAC_TSTART AT91C_EMAC_TSTART | Start Transmission. Writing one to this bit starts transmission. |
10 | EMAC_THALT AT91C_EMAC_THALT | Transmission Halt. Writing one to this bit halts transmission as soon as any ongoing frame transmission ends. |
11 | EMAC_TPFR AT91C_EMAC_TPFR | Transmit pause frame Writing one to this bit transmits a pause frame with the pause quantum from the transmit pause quantum register at the next available transmitter idle time. |
12 | EMAC_TZQ AT91C_EMAC_TZQ | Transmit zero quantum pause frame Writing a one to this bit transmits a pause frame with zero pause quantum at the next available transmitter idle time. |
Offset | Name | Description | |||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0 | EMAC_SPD AT91C_EMAC_SPD | Speed. Set to 1 to indicate 100 Mbit/sec. operation, 0 for 10 Mbit/sec. Has no other functional effect. | |||||||||||||||
1 | EMAC_FD AT91C_EMAC_FD | Full duplex. If set to 1, the transmit block ignores the state of collision and carrier sense and allows receive while transmitting. | |||||||||||||||
3 | EMAC_JFRAME AT91C_EMAC_JFRAME | Jumbo Frames. Not implemented. Set to one to enable jumbo frames of up to 10240 bytes to be accepted. | |||||||||||||||
4 | EMAC_CAF AT91C_EMAC_CAF | Copy all frames. When set to 1, all valid frames are received. | |||||||||||||||
5 | EMAC_NBC AT91C_EMAC_NBC | No broadcast. When set to 1, frames addressed to the broadcast address of all ones are not received. | |||||||||||||||
6 | EMAC_MTI AT91C_EMAC_MTI | Multicast hash event enable When set, multicast hash events causes the wol output to be asserted. | |||||||||||||||
7 | EMAC_UNI AT91C_EMAC_UNI | Unicast hash enable. When set, unicast frames are received when six bits of the CRC of the destination address point to a bit that is set in the hash register. | |||||||||||||||
8 | EMAC_BIG AT91C_EMAC_BIG | Receive 1522 bytes. When set, the MAC receives up to 1522 bytes. Normally the MAC receives frames up to 1518 bytes in length. | |||||||||||||||
9 | EMAC_EAE AT91C_EMAC_EAE | External address match enable. Optional. | |||||||||||||||
11..10 | EMAC_CLK AT91C_EMAC_CLK | The system clock (HCLK) is divided down to generate MDC (the clock for the MDIO). To conform with IEEE standard 802.3 MDC must not exceed 2.5 MHz. At reset this field is set to 10 so that HCLK is divided by 32.
| |||||||||||||||
12 | EMAC_RTY AT91C_EMAC_RTY | Retry test. When set, the time between frames is always one time slot. For test purposes only. Must be cleared for normal operation. | |||||||||||||||
13 | EMAC_PAE AT91C_EMAC_PAE | Pause Enable. When set, transmission pauses when a valid pause frame is received. | |||||||||||||||
15..14 | EMAC_RBOF AT91C_EMAC_RBOF | The system clock (HCLK) is divided down to generate MDC (the clock for the MDIO). To conform with IEEE standard 802.3 MDC must not exceed 2.5 MHz. At reset this field is set to 10 so that HCLK is divided by 32.
| |||||||||||||||
16 | EMAC_RLCE AT91C_EMAC_RLCE | Receive Length field Checking Enable When set, frames with measured lengths shorter than their length fields are discarded. | |||||||||||||||
17 | EMAC_DRFCS AT91C_EMAC_DRFCS | Discard Receive FCS When set, the FCS field of received frames are not be copied to memory. | |||||||||||||||
18 | EMAC_EFRHD AT91C_EMAC_EFRHD | Enable frames to be received in half-duplex mode while transmitting. | |||||||||||||||
19 | EMAC_IRXFCS AT91C_EMAC_IRXFCS | Ignore RX FCS When set, frames with FCS/CRC errors are not rejected and no FCS error statistics are counted. For normal operation, this bit must be set to 0. |
Offset | Name | Description |
---|---|---|
0 | EMAC_LINKR AT91C_EMAC_LINKR | Reserved |
1 | EMAC_MDIO AT91C_EMAC_MDIO | 0 = MDIO pin is not set 1 = MDIO pin set |
2 | EMAC_IDLE AT91C_EMAC_IDLE | 0 = PHY logic is idle 1 = PHY logic is running |
Offset | Name | Description |
---|---|---|
0 | EMAC_UBR AT91C_EMAC_UBR | Used Bit Read. Set when a transmit buffer descriptor is read with its used bit set. Cleared by writing a one to this bit. |
1 | EMAC_COL AT91C_EMAC_COL | Collision occurred. Set by the assertion of collision. Cleared by writing a one to this bit. |
2 | EMAC_RLES AT91C_EMAC_RLES | Retry limit exceeded. Cleared by writing a one to this bit. |
3 | EMAC_TGO AT91C_EMAC_TGO | Transmit Go Transmit Go. If high transmit is active. |
4 | EMAC_BEX AT91C_EMAC_BEX | Buffers exhausted mid frame Buffers exhausted mid frame. if the buffers run out during transmission of a frame then transmission stops, FCS shall be bad and tx_er asserted. Cleared by writing a one to this bit. |
5 | EMAC_COMP AT91C_EMAC_COMP | Transmit complete. Set when a frame has been transmitted. Cleared by writing a one to this bit. |
6 | EMAC_UND AT91C_EMAC_UND | Transmit underrun. Set when transmit DMA was not able to read data from memory in time. If this happens, the transmitter forces bad CRC. Cleared by writing a one to this bit. |
Offset | Name | Description |
---|---|---|
0 | EMAC_BNA AT91C_EMAC_BNA | Buffer not available. An attempt was made to get a new buffer and the pointer indicated that it was owned by the processor. The DMA rereads the pointer each time a new frame starts until a valid pointer is found. This bit is set at each attempt that fails even if it has not had a successful pointer read since it has been cleared. Cleared by writing a one to this bit. |
1 | EMAC_REC AT91C_EMAC_REC | Frame received. One or more frames have been received and placed in memory. Cleared by writing a one to this bit. |
2 | EMAC_OVR AT91C_EMAC_OVR | RX overrun. The DMA block was unable to store the receive frame to memory, either because the ASB bus was not granted in time or because a not OK HRESP was returned. The buffer is recovered if this happens. Cleared by writing a one to this bit. |
Offset | Name | Description |
---|---|---|
0 | EMAC_MFD AT91C_EMAC_MFD | Management Frame done. The PHY maintenance register has completed its operation. Cleared on read. |
1 | EMAC_RCOMP AT91C_EMAC_RCOMP | Receive complete. A frame has been stored in memory. Cleared on read. |
2 | EMAC_RXUBR AT91C_EMAC_RXUBR | Receive Used Bit read. Set when a receive buffer descriptor is read with its used bit set. Cleared on read. |
3 | EMAC_TXUBR AT91C_EMAC_TXUBR | Transmit Used Bit Read. Set when a transmit buffer descriptor is read with its used bit set. Cleared on read. |
4 | EMAC_TUNDR AT91C_EMAC_TUNDR | Transmit error. Ethernet transmit buffer underrun. The transmit DMA did not complete fetch frame data in time for it to be transmitted. Cleared on read. |
5 | EMAC_RLEX AT91C_EMAC_RLEX | Retry limit exceeded. Cleared on read. |
6 | EMAC_TXERR AT91C_EMAC_TXERR | Transmit buffers exhausted in mid-frame - transmit error. Cleared on read. |
7 | EMAC_TCOMP AT91C_EMAC_TCOMP | Transmit complete. Set when a frame has been transmitted. Cleared on read. |
9 | EMAC_LINK AT91C_EMAC_LINK | Set when LINK pin changes value. Optional. |
10 | EMAC_ROVR AT91C_EMAC_ROVR | RX overrun. Set when the RX overrun status bit is set. Cleared on read. |
11 | EMAC_HRESP AT91C_EMAC_HRESP | HRESP not OK. Set when the DMA block sees HRESP not OK. Cleared on read. |
12 | EMAC_PFRE AT91C_EMAC_PFRE | Indicates a valid pause has been received. Cleared on a read. |
13 | EMAC_PTZ AT91C_EMAC_PTZ | set when the pause time register, 0x38 decrements to zero. Cleared on a read. |
Offset | Name | Description |
---|---|---|
0 | EMAC_MFD AT91C_EMAC_MFD | Management Frame done. The PHY maintenance register has completed its operation. Cleared on read. |
1 | EMAC_RCOMP AT91C_EMAC_RCOMP | Receive complete. A frame has been stored in memory. Cleared on read. |
2 | EMAC_RXUBR AT91C_EMAC_RXUBR | Receive Used Bit read. Set when a receive buffer descriptor is read with its used bit set. Cleared on read. |
3 | EMAC_TXUBR AT91C_EMAC_TXUBR | Transmit Used Bit Read. Set when a transmit buffer descriptor is read with its used bit set. Cleared on read. |
4 | EMAC_TUNDR AT91C_EMAC_TUNDR | Transmit error. Ethernet transmit buffer underrun. The transmit DMA did not complete fetch frame data in time for it to be transmitted. Cleared on read. |
5 | EMAC_RLEX AT91C_EMAC_RLEX | Retry limit exceeded. Cleared on read. |
6 | EMAC_TXERR AT91C_EMAC_TXERR | Transmit buffers exhausted in mid-frame - transmit error. Cleared on read. |
7 | EMAC_TCOMP AT91C_EMAC_TCOMP | Transmit complete. Set when a frame has been transmitted. Cleared on read. |
9 | EMAC_LINK AT91C_EMAC_LINK | Set when LINK pin changes value. Optional. |
10 | EMAC_ROVR AT91C_EMAC_ROVR | RX overrun. Set when the RX overrun status bit is set. Cleared on read. |
11 | EMAC_HRESP AT91C_EMAC_HRESP | HRESP not OK. Set when the DMA block sees HRESP not OK. Cleared on read. |
12 | EMAC_PFRE AT91C_EMAC_PFRE | Indicates a valid pause has been received. Cleared on a read. |
13 | EMAC_PTZ AT91C_EMAC_PTZ | set when the pause time register, 0x38 decrements to zero. Cleared on a read. |
Offset | Name | Description |
---|---|---|
0 | EMAC_MFD AT91C_EMAC_MFD | Management Frame done. The PHY maintenance register has completed its operation. Cleared on read. |
1 | EMAC_RCOMP AT91C_EMAC_RCOMP | Receive complete. A frame has been stored in memory. Cleared on read. |
2 | EMAC_RXUBR AT91C_EMAC_RXUBR | Receive Used Bit read. Set when a receive buffer descriptor is read with its used bit set. Cleared on read. |
3 | EMAC_TXUBR AT91C_EMAC_TXUBR | Transmit Used Bit Read. Set when a transmit buffer descriptor is read with its used bit set. Cleared on read. |
4 | EMAC_TUNDR AT91C_EMAC_TUNDR | Transmit error. Ethernet transmit buffer underrun. The transmit DMA did not complete fetch frame data in time for it to be transmitted. Cleared on read. |
5 | EMAC_RLEX AT91C_EMAC_RLEX | Retry limit exceeded. Cleared on read. |
6 | EMAC_TXERR AT91C_EMAC_TXERR | Transmit buffers exhausted in mid-frame - transmit error. Cleared on read. |
7 | EMAC_TCOMP AT91C_EMAC_TCOMP | Transmit complete. Set when a frame has been transmitted. Cleared on read. |
9 | EMAC_LINK AT91C_EMAC_LINK | Set when LINK pin changes value. Optional. |
10 | EMAC_ROVR AT91C_EMAC_ROVR | RX overrun. Set when the RX overrun status bit is set. Cleared on read. |
11 | EMAC_HRESP AT91C_EMAC_HRESP | HRESP not OK. Set when the DMA block sees HRESP not OK. Cleared on read. |
12 | EMAC_PFRE AT91C_EMAC_PFRE | Indicates a valid pause has been received. Cleared on a read. |
13 | EMAC_PTZ AT91C_EMAC_PTZ | set when the pause time register, 0x38 decrements to zero. Cleared on a read. |
Offset | Name | Description |
---|---|---|
0 | EMAC_MFD AT91C_EMAC_MFD | Management Frame done. The PHY maintenance register has completed its operation. Cleared on read. |
1 | EMAC_RCOMP AT91C_EMAC_RCOMP | Receive complete. A frame has been stored in memory. Cleared on read. |
2 | EMAC_RXUBR AT91C_EMAC_RXUBR | Receive Used Bit read. Set when a receive buffer descriptor is read with its used bit set. Cleared on read. |
3 | EMAC_TXUBR AT91C_EMAC_TXUBR | Transmit Used Bit Read. Set when a transmit buffer descriptor is read with its used bit set. Cleared on read. |
4 | EMAC_TUNDR AT91C_EMAC_TUNDR | Transmit error. Ethernet transmit buffer underrun. The transmit DMA did not complete fetch frame data in time for it to be transmitted. Cleared on read. |
5 | EMAC_RLEX AT91C_EMAC_RLEX | Retry limit exceeded. Cleared on read. |
6 | EMAC_TXERR AT91C_EMAC_TXERR | Transmit buffers exhausted in mid-frame - transmit error. Cleared on read. |
7 | EMAC_TCOMP AT91C_EMAC_TCOMP | Transmit complete. Set when a frame has been transmitted. Cleared on read. |
9 | EMAC_LINK AT91C_EMAC_LINK | Set when LINK pin changes value. Optional. |
10 | EMAC_ROVR AT91C_EMAC_ROVR | RX overrun. Set when the RX overrun status bit is set. Cleared on read. |
11 | EMAC_HRESP AT91C_EMAC_HRESP | HRESP not OK. Set when the DMA block sees HRESP not OK. Cleared on read. |
12 | EMAC_PFRE AT91C_EMAC_PFRE | Indicates a valid pause has been received. Cleared on a read. |
13 | EMAC_PTZ AT91C_EMAC_PTZ | set when the pause time register, 0x38 decrements to zero. Cleared on a read. |
Offset | Name | Description |
---|---|---|
15..0 | EMAC_DATA AT91C_EMAC_DATA | For a write operation this is written with the data to be written to the PHY. After a read operation this contains the data read from the PHY. |
17..16 | EMAC_CODE AT91C_EMAC_CODE | Must be written to 10 in accordance with IEEE standard 802.3. Reads as written. |
22..18 | EMAC_REGA AT91C_EMAC_REGA | Register address. Specifies the register in the PHY to access. |
27..23 | EMAC_PHYA AT91C_EMAC_PHYA | PHY address. Normally is 0. |
29..28 | EMAC_RW AT91C_EMAC_RW | Read/write Operation. 10 is read. 01 is write. Any other value is an invalid PHY management frame. |
31..30 | EMAC_SOF AT91C_EMAC_SOF | Must be written with 01 to make a valid PHY management frame. Conforms with IEEE standard 802.3. |
Offset | Name | Description |
---|---|---|
0 | EMAC_RMII AT91C_EMAC_RMII | Reduce MII When set, this bit enables the RMII operation mode. When reset, it selects the MII mode. |
1 | EMAC_CLKEN AT91C_EMAC_CLKEN | Clock Enable When set, this bit enables the transceiver input clock. Setting this bit to 0 reduces power consumption. |
Offset | Name | Description |
---|---|---|
15..0 | EMAC_IP AT91C_EMAC_IP | ARP request IP address Written to define the least significant 16 bits of the target IP address that is matched to generate a Wake-on-LAN event. |
16 | EMAC_MAG AT91C_EMAC_MAG | Magic packet event enable When set, magic packet events causes the wol output to be asserted. |
17 | EMAC_ARP AT91C_EMAC_ARP | ARP request event enable When set, ARP request events causes the wol output to be asserted. |
18 | EMAC_SA1 AT91C_EMAC_SA1 | Specific address register 1 event enable When set, specific address 1 events causes the wol output to be asserted. |
19 | EMAC_MTI AT91C_EMAC_MTI | Multicast hash event enable When set, multicast hash events causes the wol output to be asserted. |
Offset | Name | Description |
---|---|---|
15..0 | EMAC_REVREF AT91C_EMAC_REVREF | Read-only. After a read operation this contains the revision reference value. |
31..16 | EMAC_PARTREF AT91C_EMAC_PARTREF | Read-only. After a read operation this contains the part reference value, always 0x0001. |