Advanced Encryption Standard Peripheral

AES (AT91S_AES) 0xFFFA4000 (AT91C_BASE_AES)
Periph ID AICSymbolDescription
18 (AT91C_ID_AES)Advanced Encryption Standard 128-bit

FunctionDescription
AT91F_AES_CfgPMCEnable Peripheral clock in PMC for AES


AES Software API (AT91S_AES)

OffsetFieldDescription
0x0AES_CRControl Register
0x4AES_MRMode Register
0x10AES_IERInterrupt Enable Register
0x14AES_IDRInterrupt Disable Register
0x18AES_IMRInterrupt Mask Register
0x1CAES_ISRInterrupt Status Register
0x20AES_KEYWxR[4] (AES_KEYWxR)Key Word x Register
0x40AES_IDATAxR[4] (AES_IDATAxR)Input Data x Register
0x50AES_ODATAxR[4] (AES_ODATAxR)Output Data x Register
0x60AES_IVxR[4] (AES_IVxR)Initialization Vector x Register
0xFCAES_VRAES Version Register
0x100AES_RPR (PDC_RPR)Receive Pointer Register
0x104AES_RCR (PDC_RCR)Receive Counter Register
0x108AES_TPR (PDC_TPR)Transmit Pointer Register
0x10CAES_TCR (PDC_TCR)Transmit Counter Register
0x110AES_RNPR (PDC_RNPR)Receive Next Pointer Register
0x114AES_RNCR (PDC_RNCR)Receive Next Counter Register
0x118AES_TNPR (PDC_TNPR)Transmit Next Pointer Register
0x11CAES_TNCR (PDC_TNCR)Transmit Next Counter Register
0x120AES_PTCR (PDC_PTCR)PDC Transfer Control Register
0x124AES_PTSR (PDC_PTSR)PDC Transfer Status Register

FunctionDescription
AT91F_AES_CfgModeRegConfigure the Mode Register of the AES controller
AT91F_AES_InputDataSet Input Data x
AT91F_AES_SetCryptoKeySet Cryptographic Key x
AT91F_AES_IsInterruptMaskedTest if AES Interrupt is Masked
AT91F_AES_GetInterruptMaskStatusReturn AES Interrupt Mask Status
AT91F_AES_EnableItEnable AES interrupt
AT91F_AES_GetOutputDataGet Output Data x
AT91F_AES_GetModeRegReturn the Mode Register of the AES controller value
AT91F_AES_DisableItDisable AES interrupt
AT91F_AES_IsStatusSetTest if AES Status is Set
AT91F_AES_GetStatusReturn AES Interrupt Status
AT91F_AES_SetInitializationVectorSet Initialization Vector (or Counter) x
AT91F_AES_StartProcessingStart Encryption or Decryption
AT91F_AES_SoftResetReset AES
AT91F_AES_LoadNewSeedLoad New Seed in the random number generator

AES Register Description

AES: AT91_REG AES_CR Control Register

OffsetNameDescription
0AES_START
AT91C_AES_START
Starts Processing
0 = No effect.
1 = Start Encryption/Decryption process.
8AES_SWRST
AT91C_AES_SWRST
Software Reset
0 = No effect.
1 = Resets the AES. A software triggered hardware reset of the AES interface is performed.
16AES_LOADSEED
AT91C_AES_LOADSEED
Random Number Generator Seed Loading
0 = No effect.
1 = Loads a new seed in the random number generator used for the different countermeasures.

AES: AT91_REG AES_MR Mode Register

OffsetNameDescription
0AES_CIPHER
AT91C_AES_CIPHER
Processing Mode
0 = Decrypts Data.
1 = Encrypts Data.
7..4AES_PROCDLY
AT91C_AES_PROCDLY
Processing Delay
Processing Time = 12*(PROCDLY+1) : the Processing Time represents the clock cycles number that the AES needs to perform one encryption/decryption.
9..8AES_SMOD
AT91C_AES_SMOD
Start Mode
ValueLabelDescription
0AES_SMOD_MANUAL
AT91C_AES_SMOD_MANUAL

Manual Mode: The START bit in register AES_CR must be set to begin encryption or decryption.
1AES_SMOD_AUTO
AT91C_AES_SMOD_AUTO

Auto Mode: no action in AES_CR is necessary (cf datasheet).
2AES_SMOD_PDC
AT91C_AES_SMOD_PDC

PDC Mode (cf datasheet).
14..12AES_OPMOD
AT91C_AES_OPMOD
Operation Mode
ValueLabelDescription
0AES_OPMOD_ECB
AT91C_AES_OPMOD_ECB

ECB Electronic CodeBook mode.
1AES_OPMOD_CBC
AT91C_AES_OPMOD_CBC

CBC Cipher Block Chaining mode.
2AES_OPMOD_OFB
AT91C_AES_OPMOD_OFB

OFB Output Feedback mode.
3AES_OPMOD_CFB
AT91C_AES_OPMOD_CFB

CFB Cipher Feedback mode.
4AES_OPMOD_CTR
AT91C_AES_OPMOD_CTR

CTR Counter mode.
15AES_LOD
AT91C_AES_LOD
Last Output Data Mode
0 = No effect. In Manual and Auto modes, the DATRDY flag is cleared when at least one of the Output Data registers is read.
1 = The DATRDY flag is cleared when at least one of the Input Data Registers is written. No more Output Data Register reads is necessary between consecutive encryptions/decryptions.
18..16AES_CFBS
AT91C_AES_CFBS
Cipher Feedback Data Size
ValueLabelDescription
0AES_CFBS_128_BIT
AT91C_AES_CFBS_128_BIT

128-bit.
1AES_CFBS_64_BIT
AT91C_AES_CFBS_64_BIT

64-bit.
2AES_CFBS_32_BIT
AT91C_AES_CFBS_32_BIT

32-bit.
3AES_CFBS_16_BIT
AT91C_AES_CFBS_16_BIT

16-bit.
4AES_CFBS_8_BIT
AT91C_AES_CFBS_8_BIT

8-bit.
23..20AES_CKEY
AT91C_AES_CKEY
Countermeasure Key
This field should be written with the value 0xE to allow CTYPE field changes.
28..24AES_CTYPE
AT91C_AES_CTYPE
Countermeasure Type
Countermeasure type X is disabled (bit set to 0) or enabled (bit set to 1)
ValueLabelDescription
1AES_CTYPE_TYPE1_EN
AT91C_AES_CTYPE_TYPE1_EN

Countermeasure type 1 is enabled.
2AES_CTYPE_TYPE2_EN
AT91C_AES_CTYPE_TYPE2_EN

Countermeasure type 2 is enabled.
4AES_CTYPE_TYPE3_EN
AT91C_AES_CTYPE_TYPE3_EN

Countermeasure type 3 is enabled.
8AES_CTYPE_TYPE4_EN
AT91C_AES_CTYPE_TYPE4_EN

Countermeasure type 4 is enabled.
16AES_CTYPE_TYPE5_EN
AT91C_AES_CTYPE_TYPE5_EN

Countermeasure type 5 is enabled.

AES: AT91_REG AES_IER Interrupt Enable Register

OffsetNameDescription
0AES_DATRDY
AT91C_AES_DATRDY
DATRDY
0 = No effect.
1 = En/Dis/Mask/Status of DATRDY (for Manual and Auto Mode in AES_MR).
1AES_ENDRX
AT91C_AES_ENDRX
PDC Read Buffer End
0 = The Receive Counter Register has not reached 0 since the last write in AES_RCR or AES_RNCR.
1 = The Receive Counter Register has reached 0 since the last write in AES_RCR or AES_RNCR.
2AES_ENDTX
AT91C_AES_ENDTX
PDC Write Buffer End
0 = The Transmit Counter Register has not reached 0 since the last write in AES_TCR or AES_TNCR.
1 = The Transmit Counter Register has reached 0 since the last write in AES_TCR or AES_TNCR.
3AES_RXBUFF
AT91C_AES_RXBUFF
PDC Read Buffer Full
0 = AES_RCR or AES_RNCR has a value other than 0.
1 = Both AES_RCR and AES_RNCR has a value of 0.
4AES_TXBUFE
AT91C_AES_TXBUFE
PDC Write Buffer Empty
0 = AES_TCR or AES_TNCR has a value other than 0.
1 = Both AES_TCR and AES_TNCR has a value of 0.
8AES_URAD
AT91C_AES_URAD
Unspecified Register Access Detection
0 = No unspecified register access has been detected since the last SWRST.
1 = At least one unspecified register access has been detected since the last SWRST.

AES: AT91_REG AES_IDR Interrupt Disable Register

OffsetNameDescription
0AES_DATRDY
AT91C_AES_DATRDY
DATRDY
0 = No effect.
1 = En/Dis/Mask/Status of DATRDY (for Manual and Auto Mode in AES_MR).
1AES_ENDRX
AT91C_AES_ENDRX
PDC Read Buffer End
0 = The Receive Counter Register has not reached 0 since the last write in AES_RCR or AES_RNCR.
1 = The Receive Counter Register has reached 0 since the last write in AES_RCR or AES_RNCR.
2AES_ENDTX
AT91C_AES_ENDTX
PDC Write Buffer End
0 = The Transmit Counter Register has not reached 0 since the last write in AES_TCR or AES_TNCR.
1 = The Transmit Counter Register has reached 0 since the last write in AES_TCR or AES_TNCR.
3AES_RXBUFF
AT91C_AES_RXBUFF
PDC Read Buffer Full
0 = AES_RCR or AES_RNCR has a value other than 0.
1 = Both AES_RCR and AES_RNCR has a value of 0.
4AES_TXBUFE
AT91C_AES_TXBUFE
PDC Write Buffer Empty
0 = AES_TCR or AES_TNCR has a value other than 0.
1 = Both AES_TCR and AES_TNCR has a value of 0.
8AES_URAD
AT91C_AES_URAD
Unspecified Register Access Detection
0 = No unspecified register access has been detected since the last SWRST.
1 = At least one unspecified register access has been detected since the last SWRST.

AES: AT91_REG AES_IMR Interrupt Mask Register

OffsetNameDescription
0AES_DATRDY
AT91C_AES_DATRDY
DATRDY
0 = No effect.
1 = En/Dis/Mask/Status of DATRDY (for Manual and Auto Mode in AES_MR).
1AES_ENDRX
AT91C_AES_ENDRX
PDC Read Buffer End
0 = The Receive Counter Register has not reached 0 since the last write in AES_RCR or AES_RNCR.
1 = The Receive Counter Register has reached 0 since the last write in AES_RCR or AES_RNCR.
2AES_ENDTX
AT91C_AES_ENDTX
PDC Write Buffer End
0 = The Transmit Counter Register has not reached 0 since the last write in AES_TCR or AES_TNCR.
1 = The Transmit Counter Register has reached 0 since the last write in AES_TCR or AES_TNCR.
3AES_RXBUFF
AT91C_AES_RXBUFF
PDC Read Buffer Full
0 = AES_RCR or AES_RNCR has a value other than 0.
1 = Both AES_RCR and AES_RNCR has a value of 0.
4AES_TXBUFE
AT91C_AES_TXBUFE
PDC Write Buffer Empty
0 = AES_TCR or AES_TNCR has a value other than 0.
1 = Both AES_TCR and AES_TNCR has a value of 0.
8AES_URAD
AT91C_AES_URAD
Unspecified Register Access Detection
0 = No unspecified register access has been detected since the last SWRST.
1 = At least one unspecified register access has been detected since the last SWRST.

AES: AT91_REG AES_ISR Interrupt Status Register

OffsetNameDescription
0AES_DATRDY
AT91C_AES_DATRDY
DATRDY
0 = No effect.
1 = En/Dis/Mask/Status of DATRDY (for Manual and Auto Mode in AES_MR).
1AES_ENDRX
AT91C_AES_ENDRX
PDC Read Buffer End
0 = The Receive Counter Register has not reached 0 since the last write in AES_RCR or AES_RNCR.
1 = The Receive Counter Register has reached 0 since the last write in AES_RCR or AES_RNCR.
2AES_ENDTX
AT91C_AES_ENDTX
PDC Write Buffer End
0 = The Transmit Counter Register has not reached 0 since the last write in AES_TCR or AES_TNCR.
1 = The Transmit Counter Register has reached 0 since the last write in AES_TCR or AES_TNCR.
3AES_RXBUFF
AT91C_AES_RXBUFF
PDC Read Buffer Full
0 = AES_RCR or AES_RNCR has a value other than 0.
1 = Both AES_RCR and AES_RNCR has a value of 0.
4AES_TXBUFE
AT91C_AES_TXBUFE
PDC Write Buffer Empty
0 = AES_TCR or AES_TNCR has a value other than 0.
1 = Both AES_TCR and AES_TNCR has a value of 0.
8AES_URAD
AT91C_AES_URAD
Unspecified Register Access Detection
0 = No unspecified register access has been detected since the last SWRST.
1 = At least one unspecified register access has been detected since the last SWRST.
14..12AES_URAT
AT91C_AES_URAT
Unspecified Register Access Type Status
Only the last Unspecified Register Access Type is available through the URAT field.
ValueLabelDescription
0AES_URAT_IN_DAT_WRITE_DATPROC
AT91C_AES_URAT_IN_DAT_WRITE_DATPROC

Input data register written during the data processing in PDC mode.
1AES_URAT_OUT_DAT_READ_DATPROC
AT91C_AES_URAT_OUT_DAT_READ_DATPROC

Output data register read during the data processing.
2AES_URAT_MODEREG_WRITE_DATPROC
AT91C_AES_URAT_MODEREG_WRITE_DATPROC

Mode register written during the data processing.
3AES_URAT_OUT_DAT_READ_SUBKEY
AT91C_AES_URAT_OUT_DAT_READ_SUBKEY

Output data register read during the sub-keys generation.
4AES_URAT_MODEREG_WRITE_SUBKEY
AT91C_AES_URAT_MODEREG_WRITE_SUBKEY

Mode register written during the sub-keys generation.
5AES_URAT_WO_REG_READ
AT91C_AES_URAT_WO_REG_READ

Write-only register read access.

AES: AT91_REG AES_KEYWxR Key Word x Register


Key Word x: The four 32-bit Key registers allow to set the 128-bit cryptographic key used for encryption/decryption.

AES: AT91_REG AES_IDATAxR Input Data x Register


The four 32-bit Input Data registers allow to set the 128-bit data block used for encryption/decryption.

AES: AT91_REG AES_ODATAxR Output Data x Register


The four 32-bit Output Data registers contain the 128-bit data block which has been encrypted/decrypted.

AES: AT91_REG AES_IVxR Initialization Vector x Register


The four 32-bit Initialization Vector registers allow to set the 128-bit Initialization Vector data block, which is used by some modes of operation as an additional initial input.

AES: AT91_REG AES_VR AES Version Register

AES: AT91S_PDC AES_PDC PDC interface